Investigating the effects of the interface defects on the gate leakage current in MOSFETs

The effects of the interface defects on the gate leakage current have been numerically modeled. The results demonstrate that the shallow and deep traps have different effects on the dependence relation of the stress-induced leakage current on the oxide electric field in the regime of direct tunneling, whereas both traps keep the same dependence relation in the regime of Fowler-Nordheim tunneling. The results also shows that the stress-induced leakage current will be the largest at a moderate oxide voltage for the electron interface traps but it increases with the decreasing oxide voltage for the hole interface traps. The results illustrate that the stress-induced leakage current strongly depends on the location of the electron interface traps but it weakly depends on the location of the hole interface traps. The increase in the gate leakage current caused by the electron interface traps can predict the increase, then decrease in the stress-induced leakage current, with decreasing oxide thickness, which is observed experimentally. And the electron interface trap level will have a large effect on the peak height and position.     

深亚微米器件沟道长度对总剂量辐照效应的影响

研究了180 nm 互补金属氧化物半导体技术下的器件沟道长度对总剂量辐照效应的影响. 在其他条件如辐照偏置、器件结构等不变的情况下, 氧化层中的陷阱电荷决定了辐照响应. 浅沟槽隔离氧化层中的陷阱电荷使得寄生的侧壁沟道反型, 从而形成大的关态泄漏电流. 这个电流与沟道长度存在一定的关系, 沟道长度越短, 泄漏电流越大. 首次发现辐照会增强这个电流的沟道长度调制效应, 从而使得器件进一步退化.     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.     

Dark currents in bulk heterojunction devices for imaging applications: The effect of a cathode interfacial layer

While sol–gel-processed metal oxides are widely used as an electron transport layer to enhance photovoltaic performances, their effect on photodetector application was not studied. We found sol–gel-processed titanium oxide deteriorated dark current characteristics in reverse biases by almost two orders of magnitude, whereas bare Al cathodes exhibited ideal dark current characteristics. Increased dark current came from space charge limited currents in microscopic p-i-p metal-semiconductor-metal configurations. The spatial variation of workfunction values was believed to form local leakage paths by partial filling of traps on the surface of sol–gel titanium oxide.     

0.18 μm MOSFET器件的总剂量辐照效应

对0.18 μm metal-oxide-semiconductor field-effect-transistor (MOSFET)器件进行γ射线辐照实验,讨论分析器件辐照前后关态漏电流、阈值电压、跨导、栅电流、亚阈值斜率等特性参数的变化,研究深亚微米器件的总剂量效应. 通过在隔离氧化物中引入等效陷阱电荷,三维模拟结果与实验结果符合很好. 深亚微米器件栅氧化层对总剂量辐照不敏感,浅沟槽隔离氧化物是导致器件性能退化的主要因素. 关键词： 总剂量效应 浅沟槽隔离 氧化层陷阱正电荷 MOSFET     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing(MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing(PDA) times. The equivalent oxide thickness(EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore,the characteristics of SILC(stress-induced leakage current) for an ultra-thin SiO_2/HfO_2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

闪速存储器中应力诱生漏电流的产生机理

通过实验研究了闪速存储器存储单元中应力诱生漏电流(SILC)的产生机理. 研究结果表明，在低电场应力下，其可靠性问题主要是由载流子在氧化层里充放电引起，而在高电场下，陷阱和正电荷辅助的隧穿效应导致浮栅电荷变化是引起闪速存储器失效的主要原因. 分别计算了高场应力和低场应力两种情况下SILC中的稳态电流和瞬态电流的大小. 关键词： 闪速存储器 应力诱生漏电流 电容耦合效应 可靠性     

Effect of surface roughness on leakage current and corrosion resistance of oxide layer on AZ91 Mg alloy prepared by plasma electrolytic oxidation

The influence of the surface roughness of Mg alloys on the electrical properties and corrosion resistance of oxide layers obtained by plasma electrolytic oxidation (PEO) were studied. The leakage current in the insulating oxide layer was enhanced by increasing the surface roughness, which is a favorable characteristic for the material when applied to hand-held electronic devices. The variation of corrosion resistance with surface roughness was also investigated. The corrosion resistance was degraded by the increasing surface roughness, which was confirmed with DC polarization and impedance spectroscopy. Pitting corrosion on the passive oxide layer was also analyzed with a salt spray test, which showed that the number of pits was not affected by the surface roughness when the spray time reached 96 h.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Bias dependence of a deep submicron NMOSFET response to total dose irradiation

Deep submicron n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with shallow trench isolation (STI) are exposed to ionizing dose radiation under different bias conditions.The total ionizing dose radiation induced subthreshold leakage current increase and the hump effect under four different irradiation bias conditions including the worst case (ON bias) for the transistors are discussed.The high electric fields at the corners are partly responsible for the subthreshold hump effect.Charge trapped in the isolation oxide,particularly at the Si/SiO 2 interface along the sidewalls of the trench oxide creates a leakage path,which becomes a dominant contributor to the offstate drain-to-source leakage current in the NMOSFET.Non-uniform charge distribution is introduced into a threedimensional (3D) simulation.Good agreement between experimental and simulation results is demonstrated.We find that the electric field distribution along with the STI sidewall is important for the radiation effect under different bias conditions.     

Cellular automata for nanometer-scale computation

Cellular automata have recently been proposed as an architecture for dense, locally-interacting arrays of submicron devices. However, because conventional von Neumann cellular automata do not correctly reflect the long-range behavior of typical inter-device interactions, they do not provide a suitable theoretical model for the proposed device arrays. In this paper we define replica cellular automata, a class of cellular automata that can be generated from lattice-gas cellular automata. We show that for inter-device interactions that have a well-defined screening length D, replica cellular automata provide a suitable formal model. As an example of their applicability, we exhibit a computation-universal cellular automata architecture in which the cells consist of charge-transfer quantum dot devices.     

Leakage currents in thin ferroelectric films

The basic mechanisms of leakage current components of thin lead zirconate titanate (PZT) ferroelectric films grown by the sol-gel method have been studied. Characteristic regions of current-voltage characteristics with different charge transport mechanisms have been determined. It has been shown that there is an intermediate region which separates such regions. In one of them, the leakage current depends on properties of the contact of electrodes with PZT film at low voltages; in the other, the leakage current is controlled by intrinsic properties of the PZT film bulk, and the basic mechanism of charge transport is Poole-Frenkel emission. In the intermediate region, a stepwise change in the current has been observed, which is caused by relaxing breakdown of the Schottky barrier. Time dependences of the leakage currents have been determined. It has been shown that the leakage current decreases with increasing delay time before the Schottky barrier breakdown, and the dependence becomes opposite in character after the breakdown.     

Effect of nitrogen doping on the properties of AlSiO film for wide bandgap semiconductors

A gate insulator film with a wide bandgap and a high dielectric constant is required to achieve high-power field effect transistors (FET) using wide bandgap semiconductors such as SiC, GaN, and diamond. It is observed that an aluminum silicon oxide (AlSiO) film containing 11% nitrogen has a high resistivity of 5 × 10¹⁵ Ω cm, and the leakage current of a nitrogen-doped aluminum silicon oxide (AlSiON) film is also suppressed at high temperature, as compared to the AlSiO film. For example, the leakage current at 240 °C is four orders of magnitude smaller than that of the AlSiO film, suggesting that the AlSiON film is applicable to high temperature operation of wide bandgap semiconductor devices.     

An oxide/silicon core/shell nanowire metal-oxide semiconductor field-effect transistor

This paper studies an oxide/silicon core/shell nanowire MOSFET(OS-CSNM).Through three-dimensional device simulations,we have demonstrated that the OS-CSNM has a lower leakage current and higher I on /I off ratio after introducing the oxide core into a traditional nanowire MOSFET(TNM).The oxide/silicon OS-CSNM structure suppresses threshold voltage roll-off,drain induced barrier lowering and subthreshold swing degradation.Smaller intrinsic device delay is also observed in OS-CSNM in comparison with that of TNM.     

Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

Enhancement of deposition rate of titanium silicon oxide films on silicon using hexafluorotitanic acid by nitric acid

The deposition of titanium silicon oxide films on silicon using hexafluorotitanic acid and boric acid as sources is much enhanced by nitric acid incorporation. The deposition delay time is almost zero. The structure of the films is titanium silicon oxide examined by Fourier transform infrared spectrometer. By current-voltage measurement, the leakage current of the as-deposited film with a thickness of 458 Å is about 7.78×10^-6 Å/cm² at the electrical field of 1 MV/cm. By capacitance-voltage measurement, the effective oxide charge of the as-deposited film is 6.31×10¹⁰ cm^-2. The static dielectric constant and refractive index are about 13 and 1.98, respectively. Compared with that without nitric acid incorporation, the lower effective oxide charge is from a sharp interface due to in-situ etching of nitric acid. The higher leakage current is from the higher deposition rate and the higher dielectric constant is from higher titanium content. PACS 77.84.-s     

Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier: an improved Schottky rectifier with better reverse characteristics

An improved structure of Schottky rectifier,called a trapezoid mesa trench metal-oxide semiconductor (MOS) barrier Schottky rectifier (TM-TMBS),is proposed and studied by two-dimensional numerical simulations.Both forward and especially better reverse I-V characteristics,including lower leakage current and higher breakdown voltage,are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier (TMBS) as well as a conventional planar Schottky barrier diode rectifier.Optimized device parameters corresponding to the requirement for high breakdown voltage are given.With optimized parameters,TM-TMBS attains a breakdown voltage of 186 V,which is 6.3% larger than that of the optimized TMBS,and a leakage current of 4.3×10 6 A/cm 2,which is 26% smaller than that of the optimized TMBS.The relationship between optimized breakdown voltage and some device parameters is studied.Explanations and design rules are given according to this relationship.