非线性时变系统自适应backstepping学习控制

针对含有混合未知参数的高阶非线性系统,利用backstepping方法,提出了一种自适应重复学习控制方法,该方法与分段积分机制相结合,可以处理时变参数在一个未知紧集内周期性快时变的非线性系统,通过构造微分-差分参数自适应律,设计了一种自适应控制策略,使跟踪误差在误差平方范数意义下渐近收敛于零,利用Lyapunov泛函,给出了闭环系统收敛的一个充分条件.实例仿真结果说明了该方法的有效性.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures

Current transport mechanism in Ni-germanide/n-type Ge Schottky diodes is investigated using current--voltage characterisation technique with annealing temperatures from 300~\duto 500~\du. Based on the current transport model, a simple method to extract parameters of the NiGe/Ge diode is presented by using the $I$--$V$ characteristics. Parameters of NiGe/n-type Ge Schottky diodes fabricated for testing in this paper are as follows: the ideality factor $n$, the series resistance $R_{\rm s}$, the zero-field barrier height $\phi _{\rm b0}$, the interface state density $D_{\rm it}$, and the interfacial layer capacitance $C_{\rm i}$. It is found that the ideality factor $n$ of the diode increases with the increase of annealing temperature. As the temperature increases, the interface defects from the sputtering damage and the penetration of metallic states into the Ge energy gap are passivated, thus improving the junction quality. However, the undesirable crystallisations of Ni-germanide are observed together with NiGe at a temperature higher than 400~\du. Depositing a very thin ($\sim $1~nm) heavily Ge-doped $n^{+}$ Ge intermediate layer can improve the NiGe film morphology significantly.