Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.     

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10~(11)/cm~2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

Comparison between N_2 and O_2 anneals on the integrity of an Al_2O_3/Si_3N_4/SiO_2/Si memory gate stack

In this paper the endurance characteristics and trap generation are investigated to study the effects of different postdeposition anneals(PDAs) on the integrity of an Al2O3/Si3N4/SiO2/Si memory gate stack. The flat-band voltage(Vfb)turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfbin the programmed state of the O2-PDA device keeps increasing with increasing program/erase(P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.     

Improved charge trapping flash device with Al2O3/HfSiO stack as blocking layer

In this paper, we investigate an Al₂O₃/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon-type (MONOS) memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al₂O₃/HfO₂ stack as the blocking layer, the sample with the Al₂O₃/HfSiO stack as the blocking layer shows high program/erase (P/E) speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al₂O₃/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.     

Improved characteristics for MOHOS memory with oxygen-rich GdO as charge storage layer annealed by NH3

Characteristics of metal–oxide–high-k–oxide–silicon (MOHOS) memories with oxygen-rich or oxygen-deficient GdO as charge storage layer annealed by NH₃ or N₂ are investigated. Transmission electron microscopy, X-ray photoelectron spectroscopy and X-ray diffraction are used to analyze the cross-sectional quality, composition and crystallinity, respectively, of the stacked gate dielectric with a structure of Al/Al₂O₃/GdO/SiO₂/Si. The MOHOS capacitor with oxygen-rich GdO annealed in NH₃ exhibits a good trade-off among its memory properties: large memory window (4.8 V at ±12 V, 1 s), high programming speed (2.6 V at ±12 V/100 μs), good endurance and retention properties (window degradation of 5 % after 10⁵ program/erase cycles and charge loss of 18.6 % at 85 °C after 10 years, respectively) due to passivation of oxygen vacancies, generation of deep-level traps in the grain boundaries of the GdO layer and suppression of the interlayer between GdO and SiO₂ by the NH₃ annealing.     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO₂ heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 ℃. Compared to a single p-SnO or n-SnO₂ charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO₂/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at -8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO₂, and the formation of a built-in electric field in the heterojunction.     

55 nm硅-氧化硅-氮化硅-氧化硅-硅闪存单元的γ射线和X射线电离总剂量效应研究

基于~(60)Co-γ射线和10 keV X射线辐射源,系统地研究了55 nm硅-氧化硅-氮化硅-氧化硅-硅闪存单元的电离总剂量效应,并特别关注其电学特性退化的规律与物理机制.总剂量辐照引起闪存单元I-V特性曲线漂移、存储窗口变小和静态电流增大等电学特性的退化现象,并对其数据保持能力产生影响.编程态闪存单元的I_d-V_g曲线在辐照后显著负向漂移,而擦除态负向漂移幅度较小.对比两种射线辐照,擦除态的I_d-V_g曲线漂移方向不同.相比于擦除态,富含存储电子的编程态对总剂量辐照更为敏感;且相比于~(60)Co-γ射线,本文观测到了显著的X射线剂量增强效应.利用TCAD和Geant 4工具,从能带理论详细讨论了55 nm硅-氧化硅-氮化硅-氧化硅-硅闪存单元电离总剂量效应和损伤的物理机制,并模拟和深入分析了X射线的剂量增强效应.     

Investigating the effects of the interface defects on the gate leakage current in MOSFETs

The effects of the interface defects on the gate leakage current have been numerically modeled. The results demonstrate that the shallow and deep traps have different effects on the dependence relation of the stress-induced leakage current on the oxide electric field in the regime of direct tunneling, whereas both traps keep the same dependence relation in the regime of Fowler-Nordheim tunneling. The results also shows that the stress-induced leakage current will be the largest at a moderate oxide voltage for the electron interface traps but it increases with the decreasing oxide voltage for the hole interface traps. The results illustrate that the stress-induced leakage current strongly depends on the location of the electron interface traps but it weakly depends on the location of the hole interface traps. The increase in the gate leakage current caused by the electron interface traps can predict the increase, then decrease in the stress-induced leakage current, with decreasing oxide thickness, which is observed experimentally. And the electron interface trap level will have a large effect on the peak height and position.     

LaON/SiO2和HfON/SiO2双隧穿层MONOS存储器存储特性的比较

本文对比研究了LaON/SiO₂和HfON/SiO₂双隧穿层MONOS存储器的存储特性. 实验结果表明,LaON/SiO₂双隧穿层MONOS存储器具有较大的存储窗口,快的编程/擦除速度及好的疲劳和保持特性. 其机理在于LaON较大的介电常数有效提高了编程/擦除过程中载流子的注入效率,较小的O 扩散系数减少了界面陷阱,从而减少了保持期间存储电荷通过陷阱辅助隧穿的泄漏. 而且N的结合在界面附近形成了强的La-N,Hf-N 和O-N键,可有效降低编程/擦除循环应力对界面的损伤,使器件具有好的疲劳特性. 此外,研究了退火温度对存储特性的影响,结果表明800 ℃退火样品的存储特性比700 ℃退火的好,这是因为800 ℃时NO退火可在LaON（HfON）中引入更多的N,且能更好释放应力,使介质中缺陷减少. 关键词： MONOS 双隧穿层 LaON HfON     

LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al₂O₃/LaTiON-LaON/SiO₂/Si (band-engineered MONOS) capacitors. The physical properties of the high-k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-μs +6 V), and smaller charge loss rate at 125 °C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO₂ (2.3 eV).     

Amphoteric trap modeling of multidielectric scaled SONOS nonvolatile memory structures

We have characterized multidielectric scaled SONOS nonvolatile memory structures with the quasi-static linear voltage ramp (LVR) technique and dynamic pulse measurements. We have formulated physically-based ERASE/WRITE and retention methods with deep level amphoteric traps which capture and emit carriers to the bands in the silicon nitride film. Amphoteric trap parameters are extracted by the LVR technique. ERASE/WRITE and retention amphoteric trap model simulations agree well with the experimental dynamic pulse measurements. Experimental scaled SONOS structures have been fabricated with tunnel oxide X_OT=20 Å, nitride X_N=30 Å and blocking oxide X_OB=55 Å and demonstrated a static flatband shift of 3.6 V with ±5 V programming voltages. These structures may be used as the nonvolatile memory element in high density VLSI circuits.     

A simple and accurate method for measuring program/erase speed in a memory capacitor structure

With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.     

A simple and accurate method to measure program/erase speed in a memory capacitor structure

With the merits of simple process and short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier related program/erase speed is in agreement with the reported value in a transistor structure.     

Formation of high density TiN nanocrystals and its application in non-volatile memories

Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.     

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

In this work, the trap-assisted tunneling(TAT) mechanism is modeled as a two-step physical process for charge trapping memory(CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.     

HDC: An adaptive buffer replacement algorithm for NAND flash memory-based databases

This paper proposes an adaptive buffer replacement algorithm for NAND flash memory-based databases, which is called HDC. HDC introduces an efficient replacing index for selecting pages to be evicted. This replacing index considers two factors: the hot degree of each page and the cost of writing the victim page back to NAND flash memory. It can adaptively change the weight of each factor according to the cost ratio of NAND flash memory. HDC also introduces an efficient partial update scheme, which only writes the dirty data within the dirty victim page back to NAND flash memory for further reducing the number of write operations and writes the dirty data to the free block with the lowest erase count for improving the wear-leveling degree of NAND flash memory. We conduct trace-driven simulations on two kinds of NAND flash memories the cost ratios of which are 118:1 and 2:1. The experimental results show that HDC outperforms the state-of-the-art algorithms on both these kinds of NAND flash memories.     

Influence of excess Si distribution in the gate oxide on the memory characteristics of MOSFETs

In this work, Si ions are implanted into the gate oxide of MOSFETs with different implantation schemes, followed by a high-temperature annealing. The memory characteristics of the MOSFETs have been investigated for the following two excess Si distributions: (1) the excess Si is distributed in a narrow layer in the gate oxide near the Si substrate; and (2) the excess Si is distributed throughout the gate oxide. It is observed that both the excess Si distributions have good endurance of up to 10⁶ program/erase cycles. The second excess Si distribution exhibits a better retention characteristic with less than 50% charge loss after 10 years. In contrast, the first excess Si distribution shows a complete charge loss after 1 year. PACS 73.22.-f; 73.63.Bd; 81.07.Bc     

Charge storage characteristics in Al/AlN/Si metal–insulator–semiconductor structure based on deep traps in AlN layer

Charge storage characteristics in an Al/AlN/p-Si metal–insulator–semiconductor (MIS) structure have been investigated by capacitance–voltage and long-term capacitance measurements. Good program/erase behavior is observed in the AlN/Si structure, which is attributed to the trapping and detrapping of charges in deep traps of the AlN layer. In the long-term retention mode, a clear memory window is found 2000 s after removing a program/erase voltage of ±3 V, indicating good charge retention capability of the MIS structure. Further investigation shows that for a program pulse width of 500 ms, the charge storage does not occur when the pulse amplitude is smaller than a threshold value of ∼1 V. The trapped charge density increases linearly with increase of the pulse amplitude (>1 V) and tends to saturate at 2.5 V. With increasing program pulse width, the trapped charged density increases a little more than logarithmically. PACS 73.40.Kp; 72.20.Jv; 71.55.Eq