Interface states in Al2O3/AlGaN/GaN metal-oxide-semiconductor structure by frequency dependent conductance technique

Frequency dependent conductance measurements are implemented to investigate the interface states in Al2O3/AlGaN/GaN metal-oxide-semiconductor(MOS) structures. Two types of device structures, namely, the recessed gate structure(RGS) and the normal gate structure(NGS), are studied in the experiment. Interface trap parameters including trap density Dit, trap time constant τit, and trap state energy ETin both devices have been determined. Furthermore,the obtained results demonstrate that the gate recess process can induce extra traps with shallower energy levels at the Al2O3/AlGaN interface due to the damage on the surface of the AlGaN barrier layer resulting from reactive ion etching(RIE).     

Low specific on-resistance GaN-based vertical heterostructure field effect transistors with nonuniform doping superjunctions

A novel Ga N-based vertical heterostructure field effect transistor(HFET) with nonuniform doping superjunctions(non-SJ HFET) is proposed and studied by Silvaco-ATLAS,for minimizing the specific on-resistance(R_(on)A) at no expense of breakdown voltage(BV).The feature of non-SJ HFET lies in the nonuniform doping concentration from top to bottom in the n-and p-pillars,which is different from that of the conventional Ga N-based vertical HFET with uniform doping superjunctions(un-SJ HFET).A physically intrinsic mechanism for the nonuniform doping superjunction(non-SJ) to further reduce R_(on)A at no expense of BV is investigated and revealed in detail.The design,related to the structure parameters of non-SJ,is optimized to minimize the R_(on)A on the basis of the same BV as that of un-SJ HFET.Optimized simulation results show that the reduction in R_(on)A depends on the doping concentrations and thickness values of the light and heavy doping parts in non-SJ.The maximum reduction of more than 51% in R_(on)A could be achieved with a BV of 1890 V.These results could demonstrate the superiority of non-SJ HFET in minimizing R_(on)A and provide a useful reference for further developing the Ga N-based vertical HFETs.     

Effects of Annealing on Schottky Characteristics in A1GaN/GaN HEMT with Transparent Gate Electrode

A1GaN/GaN heterostructure transistors are promising for power and switching applications. In addition, the transparent wide band-gap A1GaN/GaN heterostructure systems have received considerable attention to transparent electronics. Nowdays, Al-doped ZnO （AZO） thin film plays an increas- ingly important role in various fields of transparent electronics.The AZO-gated A1GaN/GaN HEMT with good dc characteristics and frequency character- istics has been reported. Annealing is widely used to improve the electri- cal characteristics of A1GaN/GaN HEMTs. It is re- ported that the Schottky leakage current can be re- duced by over four orders of magnitude by annealing in an A1GaN/GaN heterostructure with ITO/Ni/Au electrode. Pei et al. reported that the transparency of Ni/ITO gates of A1GaN/GaN HEMTs has been sig- nificantly improved after annealing. However, the evaluation of Schottky C V characteristics was ab- sent. Up to now, few results are reported on the Schot- tky annealing characteristics of AZO in A1GaN/GaN HEMT. Thus the effects of annealing on the leakage current, transparency and interface states character- istics need further study.     

闪速存储器中应力诱生漏电流的产生机理

通过实验研究了闪速存储器存储单元中应力诱生漏电流(SILC)的产生机理. 研究结果表明，在低电场应力下，其可靠性问题主要是由载流子在氧化层里充放电引起，而在高电场下，陷阱和正电荷辅助的隧穿效应导致浮栅电荷变化是引起闪速存储器失效的主要原因. 分别计算了高场应力和低场应力两种情况下SILC中的稳态电流和瞬态电流的大小. 关键词： 闪速存储器 应力诱生漏电流 电容耦合效应 可靠性     

Channel temperature determination of a multifinger AlGaN/GaN high electron mobility transistor using a micro-Raman technique

Self-heating in a multifinger AlGaN/GaN high electron mobility transistor (HEMT) is investigated by micro-Raman spectroscopy. The device temperature is probed on the die as a function of applied bias. The operating temperature of the AlGaN/GaN HEMT is estimated from the calibration curve of a passively heated AlGaN/GaN structure. A linear increase of junction temperature is observed when direct current dissipated power is increased. When the power dissipation is 12.75 W at a drain voltage of 15 V, a peak temperature of 69.1°C is observed at the gate edge on the drain side of the central finger. The position of the highest temperature corresponds to the high-field region at the gate edge.     

A two-dimensional fully analytical model with polarization effect for off-state channel potential and electric field distributions of GaN-based field-plated high electron mobility transistor

In this paper, we present a two-dimensional （2D） fully analytical model with consideration of polarization effect for the channel potential and electric field distributions of the gate field-plated high electron mobility transistor （FP-HEMT） on the basis of 2D Poisson＇s solution. The dependences of the channel potential and electric field distributions on drain bias, polarization charge density, FP structure parameters, A1GaN/GaN material parameters, etc. are investigated. A simple and convenient approach to designing high breakdown voltage FP-HEMTs is also proposed. The validity of this model is demonstrated by comparison with the numerical simulations with Silvaco-Atlas. The method in this paper can be extended to the development of other analytical models for different device structures, such as MIS-HEMTs, multiple-FP HETMs, slant-FP HEMTs, etc.     

Field plate structural optimization for enhancing the power gain of GaN-based HEMTs

A novel source-connected field plate structure, featuring the same photolithography mask as the gate electrode, is proposed as an improvement over the conventional field plate (FP) techniques to enhance the frequency performance in GaN-based HEMTs. The influences of the field plate on frequency and breakdown performance are investigated simultaneously by using a two-dimensional physics-based simulation. Compared with the conventional T-gate structures with a field plate length of 1.2 μm, this field plate structure can induce the small signal power gain at 10 GHz to increase by 5-9.5 dB, which depends on the distance between source FP and dramatically shortened gate FP. This technique minimizes the parasitic capacitances, especially the gate-to-drain capacitance, showing a substantial potential for millimeter-wave, high power applications.     

Simulation design of normally-off AlGaN/GaN high-electron-mobility transistors with p-GaN Schottky hybrid gate

A novel normally-off AlGaN/GaN high-electron-mobility transistor (HEMT) with a p-GaN Schottky hybrid gate (PSHG) is proposed, and compared with the conventional p-GaN normally-off AlGaN/GaN HEMTs. This structure can be realized by selective etching of p-GaN layer, which enables the Schottky junction and PN junction to control the channel charge at the same time. The direct current (DC) and switching characteristics of the PSHG HEMTs are simulated by Slivaco TCAD, and the p-GaN HEMTs and conventional normally-on HEMTs are also simulated for comparison. The simulation results show that the PSHG HEMTs have a higher current density and a lower on-resistance than p-GaN HEMTs, which is more obvious with the decrease of p-GaN ratios of the PSHG HEMTs. The breakdown voltage and threshold voltage of the PSHG HEMTs are very close to those of the p-GaN HEMTs. In addition, the PSHG HEMTs have a higher switching speed than the conventional normally-on HEMTs, and the p-GaN layer ratio has no obvious effect on the switching speed.     

Improvement of reverse blocking performance in vertical power MOSFETs with Schottky–drain-connected semisuperjunctions

To enhance the reverse blocking capability with low specific on-resistance,a novel vertical metal-oxidesemiconductor field-effect transistor(MOSFET) with a Schottky-drian(SD) and SD-connected semisuperjunctions(SDD-semi-SJ),named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional(2D) numerical simulations.The SD contacted with the n-pillar exhibits the Schottky-contact property,and that with the p-pillar the Ohmic-contact property.Based on these features,the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions(SJ) or semisuperjunctions(semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage(BV) and the specific on-resistance(R_(on)A).For a given pillar width and n-drift thickness,there exists a proper range of n-drift concentration(N),in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of R_(on)A-BV compared to the predication of SJ MOSFET in the forward applications.And what is much valuable,in this proper range of N,the desired BV and good trade-off could be achieved only by determining the pillar thickness,with the top assist layer thickness unchanged.Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of R_(on)A-BV improvement in SD-D-semi-SJ MOSFET.These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications.     

AlGaAs/InGaAs/GaAs赝配高电子迁移晶体管的kink效应研究

利用二维器件模拟软件MEDICI对AlGaAs/InGaAs/GaAs赝配高电子迁移晶体管器(PHEMT)件进行了仿真，研究了PHEMT器件的掺杂浓度与电子浓度分布，PHEMT器件内部的电流走向及传输特性，重点研究了不同温度和不同势垒层浓度情况下PHEMT器件的kink效应.研究结果表明：kink效应主要与处于高层深能级中的陷阱俘获/反俘获过程有关，而不是只与碰撞电离有关. 关键词： 高电子迁移率晶体管 kink效应 二维电子气