纳米DDR SRAM器件重离子单粒子效应试验研究

针对90 nm和65 nm DDR（双倍数率）SRAM器件,开展与纳米尺度SRAM单粒子效应相关性的试验研究。分析了特征尺寸、测试图形、离子入射角度、工作电压等不同试验条件对单粒子翻转（SEU）的影响和效应规律,并对现有试验方法的可行性进行了分析。研究表明:特征尺寸减小导致翻转截面降低,测试图形和工作电压对器件单粒子翻转截面影响不大;随着入射角度增加,多位翻转的增加导致器件SEU截面有所增大;余弦倾角的试验方法对于纳米器件的适用性与离子种类和线性能量转移（LET）值相关,具有很大的局限性。     

基于蒙特卡洛和器件仿真的单粒子翻转计算方法

文章提出了一种基于蒙特卡洛和器件仿真的存储器单粒子翻转截面获取方法,可以准确计算存储器单粒子效应,并定位单粒子翻转的灵敏区域.基于该方法,计算了国产静态存储器和现场可编程门阵列(FPGA)存储区的单粒子效应的截面数据,仿真结果和重离子单粒子效应试验结果符合较好.仿真计算揭示了器件单粒子翻转敏感程度与器件n,p截止管区域面积相关的物理机理,并获得了不同线性能量转移(LET)值下单粒子翻转灵敏区域分布.采用蒙特卡洛方法计算了具有相同LET、不同能量的离子径迹分布,结果显示高能离子的电离径迹半径远大于低能离子,而低能离子径迹中心的能量密度却要高约两到三个数量级.随着器件特征尺寸的减小,这种差别的影响将会越来越明显,阈值LET和饱和截面将不能完全描述器件单粒子效应结果.     

The supply voltage scaled dependency of the recovery of single event upset in advanced complementary metal-oxide-semiconductor static random-access memory cells

Using computer-aided design three-dimensional simulation technology,the supply voltage scaled dependency of the recovery of single event upset and charge collection in static random-access memory cells are investigated.It reveals that the recovery linear energy transfer threshold decreases with the supply voltage reducing,which is quite attractive for dynamic voltage scaling and subthreshold circuit radiation-hardened design.Additionally,the effect of supply voltage on charge collection is also investigated.It is concluded that the supply voltage mainly affects the bipolar gain of the parasitical bipolar junction transistor(BJT) and the existence of the source plays an important role in supply voltage variation.     

Monte Carlo evaluation of spatial multiple-bit upset sensitivity to oblique incidence

We investigate the impact of heavy ion irradiation on a hypothetical static random access memory (SRAM) device. Influences of the irradiation angle, critical charge, drain-drain spacing, and dimension of device structure on the device sensitivity have been studied. These prediction and simulated results are interpreted with MUFPSA, a Monte Carlo code based on Geant4. The results show that the orientation of ion beams and device with different critical charge exert indispensable effects on multiple-bit upsets (MBUs), and that with the decrease in spacing distance between adjacent cells or the dimension of the cells, the device is more susceptible to single event effect, especially to MBUs at oblique incidence.     

Supply voltage scaled dependency of the recovery of single event upset in advanced complementary metal-oxide-semiconductor static random-access memory cells

Using the technology computer-aided design three-dimensional simulation, the supply voltage scaled dependency of the recovery of single event upset and charge collection in static random-access memory cells are investigated. It reveals that the recovery linear energy transfer threshold decreases with the supply voltage reducing, which is quite attractive to the dynamic voltage scaling and subthreshold circuits radiation-hardened design. Additionally, the effect of supply voltage on charge collection is also investigated. It is concluded that the supply voltage mainly affects the bipolar gain of parasitical bipolar junction transistor (BJT) and the existence of the source plays an important role in the supply voltage variation.     

各向异性静态随机存储器中的多位翻转分析研究

重离子实验结果表明,具有高线性能量转移(LET)或大角度入射的快重离子导致静态随机存储器(SRAM)中的多位翻转(MBU)比例增大,甚至超过单位翻转比例。单个离子径迹中的电荷可以沿着径向扩散数个微米,被临近的灵敏区收集后引起MBU。器件灵敏区的各向异性空间布局与离子入射方向共同影响测试器件的MBU图形特征。位线接触点的纵向隔离导致横向型成为主要的两位翻转图形;"L"型和"田"型分别是主要的三位翻转和四位翻转图形。最后,对SRAM抗MBU加固设计和实验验证方法进行了讨论。     

重离子在14-nm FinFET SRAM器件引起的单粒子翻转

通过重离子实验研究了14-nm FinFET工艺静态随机存取存储器(SRAM)的单粒子翻转(SEU)特性。通过使用Weibull函数拟合SEU截面获得该器件的线性能量转移(LET)阈值:0.1 MeV/(mg/cm2)。对多位翻转(MBU)贡献的统计结果表明,当LET等于40.3 MeV/(mg/cm2)时,MBU的占比超过95%。此外,FinFET SRAM的SEU截面呈现出与Fin相关的入射角度的各向异性。该研究对基于FinFET工艺的抗辐射CMOS集成电路(IC)的设计具有一定的指导作用。     

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor (NMOS) transistor or P-channel metal-oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal-oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.     

Dependence of single event upsets sensitivity of low energy proton on test factors in 65 nm SRAM

In order to accurately predict the single event upsets(SEU) rate of on-orbit proton, the influence of the proton energy distribution, incident angle, supply voltage, and test pattern on the height, width, and position of SEU peak of low energy protons(LEP) in 65 nm static random access memory(SRAM) are quantitatively evaluated and analyzed based on LEP testing data and Monte Carlo simulation. The results show that different initial proton energies used to degrade the beam energy will bring about the difference in the energy distribution of average proton energy at the surface and sensitive region of the device under test(DUT), which further leads to significant differences including the height of SEU peak and the threshold energy of SEU. Using the lowest initial proton energy is extremely important for SEU testing with low energy protons. The proton energy corresponding to the SEU peak shifts to higher average proton energies with the increase of the tilt angle, and the SEU peaks also increase significantly. The reduction of supply voltage lowers the critical charge of SEU, leading to the increase of LEP SEU cross section. For standard 6-transitor SRAM with bit-interleaving technology,SEU peak does not show clear dependence on three test patterns of logical checkerboard 55 H, all "1", and all "0". It should be noted that all the SEUs in 65 nm SRAM are single cell upset in LEP testing due to proton's low linear energy transfer(LET) value.     

单粒子翻转脉冲激光模拟的能量阈值的计算

 根据光的吸收机理,分析了单粒子效应脉冲激光模拟实验中所需用的脉冲激光的特点,探讨了脉冲激光单粒子效应的Monte Carlo计算模拟途径。在只考虑光电效应的简化下,得到存储器硅片单粒子翻转时入射脉冲激光能量阈值与临界电荷的计算关系式,进而给出该硅片的翻转截面的计算公式。在给定了存储器硅片的临界电荷的情况下,对入射脉冲激光能量阈值和单粒子翻转截面进行了计算。     

Study on the dose rate upset effect of partially depleted silicon-on-insulator static random access memory

This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM (Partially Depleted Silicon-On-Insulator Static Random Access Memory) with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM (Static Random Access Memory) chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. Specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about 1x10⁸Gy(Si)/s. However, there are few bits upset when the dose rate reaches up to 1.58x10⁹Gy(Si)/s. The SRAM circuit can still work after the high level γ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations have been taken to improve the dose rate hardened performance of the PDSOI SRAM.     

纳米静态随机存储器质子单粒子多位翻转角度相关性研究

器件特征尺寸的减小带来单粒子多位翻转的急剧增加, 对现有加固技术带来了极大挑战. 针对90 nm SRAM(static random access memory, 静态随机存储器)开展了中高能质子入射角度对单粒子多位翻转影响的试验研究, 结果表明随着质子能量的增加, 单粒子多位翻转百分比和多样性增加, 质子单粒子多位翻转角度效应与质子能量相关. 采用一种快速计算质子核反应引起单粒子多位翻转的截面积分算法, 以Geant4中Binary Cascade模型作为中高能质子核反应事件发生器, 从次级粒子的能量和角度分布出发, 揭示了质子与材料核反应产生的次级粒子中, LET(linear energy transfer)最大, 射程最长的粒子优先前向发射是引起单粒子多位翻转角度相关性的根本原因. 质子能量、临界电荷的大小是影响纳米SRAM器件质子多位翻转角度相关性的关键因素. 质子能量越小, 多位翻转截面角度增强效应越大; 临界电荷的增加将增强质子多位翻转角度效应.     

252Cf源和重离子加速器对FPGA的单粒子效应

 对10万门基于静态随机存储器的现场可编程门阵列（FPGA）分别在锎-252（²⁵²Cf）源和HI-13串列加速器下进行了单粒子效应试验研究,测试了静态单粒子翻转截面及发生单粒子闩锁的线性能量转移阈值,并对试验结果进行了等效性分析比较。试验结果表明²⁵²Cf源引起的FPGA单粒子翻转截面比重离子加速器引起的约低1个数量级;使用²⁵²Cf源未能观测到该器件的单粒子闩锁现象,而使用重离子加速器可以测出该FPGA发生单粒子闩锁的线性能量转移阈值;在现代集成电路的宇航辐射效应地面模拟单粒子效应试验中²⁵²Cf源不是理想的测试单粒子闩锁的辐射源。     

FPGA配置片反熔丝PROMs加速器地面单粒子效应特性研究

针对0.13 μm CMOS（Complementary Metal-Oxide-Semiconductor）体硅外延工艺下FPGA（Field Programmable Gate Arrays）配置片反熔丝PROM（Programmable-Read-Only-Memory）进行了单粒子效应（Single Event Effects SEEs）的加速器地面模拟试验研究。以PROM的存储容量、数据类型和工艺差异性为研究变量,考核与验证其在不同种类和能量粒子入射的系列性加速器地面SEEs模拟试验。研究结果表明,相对于8 Mbits PROM而言,空片16 Mbits PROM抗辐射性能最优,且从翻转饱和截面上说,16 Mbits的PROM具备更高的可靠性,优于国外同系列的芯片类型,试验用PROM芯片的单粒子锁定阈值>99.0 MeV·cm2/mg。另一方面,研究0.13 μm CMOS普通与深阱工艺技术下PROM芯片单粒子翻转效应异同性的实验数据表明,在高LET（Linear Energy Transfer）处的两者抗辐射性能并无明显变化,但是低LET处（LET翻转阈值）的加固效果较为明显,即抗辐射技术能力主要体现在LET翻转阈值的提升而非翻转截面的减小。Single event effects (SEEs) have been characterized and investigated on one-time configured devices for field-programmable-gate-arrays (FPGA) of programmable-read-only-memory (PROM) in 0.13 μm Complementary Metal-Oxide-Semiconductor (CMOS) technology.The variables of their memory size,written data and technology have been taken into consideration as the key parameters affecting the SEEs sensitivity when testing and verifying the reliability/radiation tolerance on self-made PROMs by heavy ions.The results show that,16 Mbits PROM within blanked data has been studied that it has better performance to radiation tolerance as compared with the 8 Mbits PROMs.Additionally,16 Mbits PROMs have the higher reliability,if based on the viewpoint of the saturated single event upset cross-section.To the single event latchup,16 Mbits PROMs were exposed to a total fluence of 107 ions/cm2 at the linear energy transfer (LET) of 99.0 MeV·cm2/mg and no obvious fluctuation of current has been observed.Additionally,as comparing the zone of high LET value,0.13 μm CMOS transistors with deep-well technology present a better radiation hardened approach than normal technology,especially in improving the threshold of LET at the zone of low LET value.     

14 nm FinFET和65 nm平面工艺静态随机存取存储器中子单粒子翻转对比

使用中国散裂中子源提供的宽能谱中子束流,开展14 nm FinFET工艺和65 nm平面工艺静态随机存取存储器中子单粒子翻转对比研究,发现相比于65 nm器件,14 nm FinFET器件的大气中子单粒子翻转截面下降至约1/40,而多位翻转比例从2.2%增大至7.6%,源于14 nm FinFET器件灵敏区尺寸(80 nm×30 nm×45 nm)、间距和临界电荷(0.05 fC)的减小.不同于65 nm器件对热中子免疫的现象,14 nm FinFET器件中M0附近10B元素的使用导致其表现出一定的热中子敏感性.进一步的中子输运仿真结果表明,高能中子在器件灵敏区中产生的大量的射程长、LET值大的高Z二次粒子是多位翻转的产生诱因,而单粒子翻转主要来自于p,He,Si等轻离子的贡献.     

Grating spacing dependence of nonvolatile holographic recording with arbitrary charge transport lengths

Grating spacing dependence of nonvolatile holographic recording in doubly doped lithium niobate crystals is theoretically investigated allowing arbitrary charge transport lengths. It is shown that the nonvolatile refractive index modulation initially increases with increasing grating spacing, then a saturation behavior arises because of the dominant bulk photovoltaic effect. Although different charge transport length results in different nonvolatile refractive index modulation, the grating spacing dependence of nonvolatile holographic recording obeys almost the same rules for arbitrary charge transport lengths. The experimental results obtained by recording nonvolatile holograms in LiNbO₃:Cu:Ce crystals with different grating spacing are consistent with the theoretical analyses.     

静态随机存储器单粒子翻转效应三维数值模拟

针对特征尺寸为1.5 μm的国产静态随机存储器（SRAM）,构建了三维SRAM存储单元模型,并对重离子引起的SRAM单粒子翻转效应进行了数值模拟.计算并分析了单粒子引起的单粒子翻转和电荷收集的物理图像,得到了SRAM器件的单粒子翻转截面曲线.单粒子翻转的数值模拟结果与重离子微束、重离子宽束实验结果比较一致,表明所建立的三维器件模型可以用来研究SRAM器件的单粒子翻转效应. 关键词： 三维数值模拟 单粒子翻转 微束 宽束     

石墨烯碳纳米管复合结构渗透特性的分子动力学研究

采用经典分子动力学方法研究了压力驱动作用下水在石墨烯碳纳米管复合结构中的渗透特性.研究结果表明,水分子渗透通过石墨烯碳纳米管复合结构的渗透率明显高于石墨烯碳纳米管组合结构.水在石墨烯碳纳米管复合结构中的渗透率随着压强的升高而增大,随着电场强度的增大而减小.考虑了温度和复合结构中双碳管轴心距对水渗透性的影响规律.系统温度越高,水的渗透率越高;随着双碳管轴心距的增加,水的渗透率逐渐降低.通过计算分析水流沿渗透方向的能障分布,解释了各参数变化对水在石墨烯碳管复合结构中渗透特性的影响机理.研究结果将为基于石墨烯碳管复合结构的新型纳米水泵设计提供一定的理论依据.     

Simulation of temporal characteristics of ion-velocity susceptibility to single event upset effect

Using a Monte Carlo simulation tool of the multi-functional package for SEEs Analysis(MUFPSA), we study the temporal characteristics of ion-velocity susceptibility to the single event upset(SEU) effect, including the deposited energy,traversed time within the device, and profile of the current pulse. The results show that the averaged dposited energy decreases with the increase of the ion-velocity, and incident ions of209 Bi have a wider distribution of energy deposition than132 Xe at the same ion-velocity. Additionally, the traversed time presents an obvious decreasing trend with the increase of ion-velocity. Concurrently, ion-velocity certainly has an influence on the current pulse and then it presents a particular regularity. The detailed discussion is conducted to estimate the relevant linear energy transfer(LET) of incident ions and the SEU cross section of the testing device from experiment and simulation and to critically consider the metric of LET.     

Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ~(129)Xe and ~(209)Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/(mg/cm~2). When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer(LET). Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ~(129)Xe ions. The percolation path between the floating-gate(FG) and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.