Experimental study of surface crystallization on integrated circuit chips

A surface crystallization phenomenon on bonding pads and wires of integrated circuit chip is reported in this paper. Through a lot of experiments, an unknown failure effect caused by mixed crystalline matter is revealed, whereas non-plasma fluorine contamination cannot cause the failure of bonding pads. By experiments combined with infrared spectroscopy analysis, the surface crystallization effect is studied. The conclusion of the study can provide the guidance for IC fabrication, modelling and analysis.     

Direct measurement and analysis of total ionizing dose effect on 130 nm PD SOI SRAM cell static noise margin

In this work, the total ionizing dose(TID) effect on 130 nm partially depleted(PD) silicon-on-insulator(SOI) static random access memory(SRAM) cell stability is measured. The SRAM cell test structure allowing direct measurement of the static noise margin(SNM) is specifically designed and irradiated by gamma-ray. Both data sides' SNM of 130 nm PD SOI SRAM cell are decreased by TID, which is different from the conclusion obtained in old generation devices that one data side's SNM is decreased and the other data side's SNM is increased. Moreover, measurement of SNM under different supply voltages(Vdd) reveals that SNM is more sensitive to TID under lower Vdd. The impact of TID on SNM under data retention Vddshould be tested, because Vddof SRAM cell under data retention mode is lower than normal Vdd.The mechanism under the above results is analyzed by measurement of I–V characteristics of SRAM cell transistors.     

Study on the dose rate upset effect of partially depleted silicon-on-insulator static random access memory

This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM (Partially Depleted Silicon-On-Insulator Static Random Access Memory) with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM (Static Random Access Memory) chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. Specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about 1x10⁸Gy(Si)/s. However, there are few bits upset when the dose rate reaches up to 1.58x10⁹Gy(Si)/s. The SRAM circuit can still work after the high level γ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations have been taken to improve the dose rate hardened performance of the PDSOI SRAM.