重离子在14-nm FinFET SRAM器件引起的单粒子翻转

通过重离子实验研究了14-nm FinFET工艺静态随机存取存储器(SRAM)的单粒子翻转(SEU)特性。通过使用Weibull函数拟合SEU截面获得该器件的线性能量转移(LET)阈值:0.1 MeV/(mg/cm2)。对多位翻转(MBU)贡献的统计结果表明,当LET等于40.3 MeV/(mg/cm2)时,MBU的占比超过95%。此外,FinFET SRAM的SEU截面呈现出与Fin相关的入射角度的各向异性。该研究对基于FinFET工艺的抗辐射CMOS集成电路(IC)的设计具有一定的指导作用。     

Geant4模拟δ电子对单粒子翻转的影响

利用Geant4蒙特卡洛程序包, 基于RPP (Rectangular ParallelePiped Volume)模型构建SRAM器件单元的灵敏体积, 编写了重离子在器件材料中的输运程序和单粒子翻转截面计算方法, 得到了简化器件结构的单粒子翻转截面σ与线性能量转移LET的关系曲线, 计算得到的翻转LET阈值和饱和截面与实验结果基本一致。模拟获得了LET值为99.69 MeV/(cm-2·mg)的Bi离子及LET值为69 MeV/(cm-2·mg)的Bi离子和Xe离子在器件材料中产生的δ电子分布图像,讨论了δ电子分布对翻转截面的影响。 计算了灵敏体积中能量沉积与δ电子分布的关系,认为δ电子分布对单粒子效应的影响随着器件的特征尺寸减小将更加严重。In this paper, the sensitive volume of SRAMs was constructed based on RPP(Rectangular ParallelePiped Volume) model using the Monte-Carlo code Geant4. The interactions of heavy ion with materials and the SEU(Single Event Upset) cross section calculation method were presented in the program. The SEU cross section curves with the linear energy deposition ware obtained. The SEU threshold value and saturation cross section were consistent with the testing data with heavy ions beam. The δ electrons distribution were different in the device material, which were generated by Bi ion with LETs of 99.67 MeV/(cm2·mg) and Bi ion, Xe ion with LETs of 69 MeV/(cm-2·mg). These results indicate δ electrons distribution impacts on the SEU cross section. According to the relation of energy deposition in the sensitive volume, the δ electrons distribution have more and more important effect on the Single Event Effect with reducing the feature size of semiconductor devices.     

深亚微米SRAM质子单粒子翻转实验研究

宇航半导体器件运行在一个复杂的空间辐射环境中,质子是空间辐射环境中粒子的重要组成部分,因而质子在半导体器件中导致的辐射效应一直受到国内外的关注。利用兰州重离子加速器(Heavy Ion Research Facility In Lanzhou) 加速出的H2 分子打靶产生能量为10 MeV 的质子,研究了特征尺寸为0.5/0.35/0.15 μm体硅和绝缘体上硅(SOI) 工艺静态随机存储器(SRAM) 的质子单粒子翻转敏感性,这也是首次在该装置上开展的质子单粒子翻转实验研究。实验结果表明特征尺寸为亚微米的SOI 工艺SRAM器件对质子单粒子翻转不敏感,但随着器件特征尺寸的减小和工作电压的降低,SOI 工艺SRAM器件对质子单粒子翻转越来越敏感;特征尺寸为深亚微米的体硅工艺SRAM器件单粒子翻转截面随入射质子能量变化明显,存在发生翻转的质子能量阈值,CREME-MC模拟结果表明质子在深亚微米的体硅工艺SRAM器件中通过质子核反应导致单粒子翻转。Microelectronic devices are used in a harsh radiation environment for space missions. Among all the reliability issues concerned, proton induced single event upset (SEU) is becoming more and more noticeable for semiconductor components exposed on space. In this work, an experimental research of SEU induced by 10 MeV proton for static random access memory (SRAM) of 0.5, 0.35 and 0.15 m feature size is carried out on HeavyIon Research Facility in Lanzhou for the rst time. The experimental results show that proton induced SEUs in submicron and deep-submicron (SRAMs) are dominated by secondary ions generated by proton nuclear reaction events. The silicon-on-insulator SRAMs characters natural radiation-hardened SEU by proton. For the deep-submicron bulk-silicon technology SRAM, the proton SEU cross section is closely related to the proton energy and there is a threshold energy for the SEU occurrence by proton indirect ionization. CREME-MC simulation indicates that the SEU events in deep-submicron SRAM are induced by the proton nuclear reaction.     

半导体器件单粒子效应的加速器模拟实验

 着重描述了应用加速器开展半导体器件的单粒子效应实验研究的方法。采用金箔散射法可以降低加速器束流几个量级，从而满足半导体器件单粒子效应实验的要求。研制的弱流质子束流测量系统和建立的质子注量均匀性测量方法解决了质子注量的准确测量问题。实验测得静态随机存取存储器的质子单粒子翻转截面为10^-7 cm²·bit^-11量级，单粒子翻转重离子LET阈值为4～8MeV·cm²/mg，重离子单粒子翻转饱和截面为10^-7 cm²·bit^-1量级。     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

环栅肖特基势垒金属氧化物半导体场效应管漏致势垒降低效应研究

结合环栅肖特基势垒金属氧化物半导体场效应管(MOSFET)结构, 通过求解圆柱坐标系下的二维泊松方程得到了表面势分布, 并据此建立了适用于低漏电压下的环栅肖特基势垒NMOSFET阈值电压模型.根据计算结果, 分析了漏电压、沟道半径和沟道长度对阈值电压和漏致势垒降低的影响, 对环栅肖特基势垒MOSFET器件以及电路设计具有一定的参考价值. 关键词： 环栅肖特基势垒金属氧化物半导体场效应管 二维泊松方程 阈值电压模型 漏致势垒降低     

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source (CSNS), single event upset (SEU) cross sections of 14 nm fin field-effect transistor (FinFET) and 65 nm quad data rate (QDR) static random-access memories (SRAMs) are obtained under different incident directions of neutrons: front, back and side. It is found that, for both technology nodes, the "worst direction" corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume. The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions. While for multiple-cell upset (MCU) sensitivity, side incidence is the worst direction, with the highest MCU ratio. The largest MCU for the 14 nm FinFET SRAM involves 8 bits. Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.     

An improved GGNMOS triggered SCR for high holding voltage ESD protection applications

Developing an electrostatic discharge(ESD) protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor(CMOS) technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor(GGNMOS) transistor triggered silicon-controlled rectifier(SCR)structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.     

纳米DDR SRAM器件重离子单粒子效应试验研究

针对90 nm和65 nm DDR（双倍数率）SRAM器件,开展与纳米尺度SRAM单粒子效应相关性的试验研究。分析了特征尺寸、测试图形、离子入射角度、工作电压等不同试验条件对单粒子翻转（SEU）的影响和效应规律,并对现有试验方法的可行性进行了分析。研究表明:特征尺寸减小导致翻转截面降低,测试图形和工作电压对器件单粒子翻转截面影响不大;随着入射角度增加,多位翻转的增加导致器件SEU截面有所增大;余弦倾角的试验方法对于纳米器件的适用性与离子种类和线性能量转移（LET）值相关,具有很大的局限性。     

Impact of energy straggle on proton-induced single event upset test in a 65-nm SRAM cell

This paper presents a simulation study of the impact of energy straggle on a proton-induced single event upset(SEU)test in a commercial 65-nm static random access memory cell. The simulation results indicate that the SEU cross sections for low energy protons are significantly underestimated due to the use of degraders in the SEU test. In contrast, using degraders in a high energy proton test may cause the overestimation of the SEU cross sections. The results are confirmed by the experimental data and the impact of energy straggle on the SEU cross section needs to be taken into account when conducting a proton-induced SEU test in a nanodevice using degraders.     

A threshold voltage model of short-channel fully-depleted recessed-source/drain(Re-S/D) SOI MOSFETs with high-k dielectric

In this paper, a surface potential based threshold voltage model of fully-depleted(FD) recessed-source/drain(Re-S/D)silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional(2D) Poisson's equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model's results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.     

高能质子单粒子翻转效应的模拟计算

在分析质子与硅反应的基础上,提出质子单粒子翻转截面理论计算模型,建立了模拟计算方法.计算得到了不同能量的高能质子在存储单元的灵敏区内沉积的能量.指出高能质子主要通过与硅反应产生的重离子在存储单元灵敏区内沉积能量,产生电荷,导致单粒子效应,得到了单粒子翻转截面与质子能量以及随临界电荷变化的关系.并将计算得到的单粒子翻转截面与实验数据进行了比较.     

Ionizing radiation effect on single event upset sensitivity of ferroelectric random access memory

The impact of ionizing radiation effect on single event upset(SEU) sensitivity of ferroelectric random access memory(FRAM) is studied in this work. The test specimens were firstly subjected to ~(60)Co γ-ray and then the SEU evaluation was conducted using ~(209)Bi ions. As a result of TID-induced fatigue-like and imprint-like phenomena of the ferroelectric material, the SEU cross sections of the post-irradiated devices shift substantially. Different trends of SEU cross section with elevated dose were also found, depending on whether the same or complementary test pattern was employed during the TID exposure and the SEU measurement.     

电离总剂量对纳米SRAM器件单粒子翻转敏感性的影响

电离总剂量（TID）与单粒子效应（SEE）是纳米SRAM器件在航天应用中的主要威胁。随着CMOS工艺的进步,两种辐射效应在纳米SRAM器件中的协同效应出现了一些新现象,有必要进一步开展深入研究。利用γ射线以及不同种类重离子对两款纳米SRAM器件开展了辐照实验,研究了不同辐照参数、测试模式以及数据图形条件下,电离总剂量对单粒子翻转（SEU）敏感性的影响。研究结果表明,γ射线辐照过后,存储单元中反相器开关阈值减小,漏电流增大,导致SRAM存储单元抗翻转能力降低,SEU截面有明显增大;未观察到"印记效应",数据图形对测试结果没有明显影响;多位翻转（MBU）比例无明显变化。     

ESD protection for the tolerant I/O circuits using PESD implantation

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call “PESD” implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μm process, this method provides a significant improvement in the cascode ESD performance.     

重离子核反应对单粒子翻转的影响（英文）

LET作为一个传统的工程参量,并不能完全满足单粒子翻转数据表征的需要,而且也不能直接地反映核反应的一些特性(包括核反应概率与次级粒子),因此研究了重离子与器件作用过程中核反应对单粒子翻转的影响。基于蒙特卡罗模拟与深入的分析,本研究对比了在直接电离与考虑核反应两种模式下的模拟结果。在模拟中,利用不同的重离子表征了核反应在单粒子翻转发生中所起的作用。结果显示,核反应对单粒子翻转截面的贡献依赖于离子的能量,并呈现非单调的变化关系。基于模拟的结果,建议用重离子核反应引起单粒子翻转的最恶劣情况来预估空间单粒子翻转率。     

The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology

ABSTRACT

As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radiation. High-performance static random access memory (SRAM) cells are prone to radiation-induced single event upsets (SEU) which come from the natural space environment. The SEU generates a soft error in the transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 130 up to 22?nm CMOS technology towards SEU. Besides that, this paper discusses the trend of critical linear energy transfer (LET) and collected charge due to technology scaling for the respective circuit. The critical LET (LETcrit) and critical charge (Qcrit) of 6T are approximately 50% lower compared with 12T SRAMs.     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

随机静态存储器低能中子单粒子翻转效应

 建立了中子单粒子翻转可视化分析方法,对不同特征尺寸（0.13~1.50 μm）CMOS工艺商用随机静态存储器(SRAM)器件开展了反应堆中子单粒子翻转效应的实验研究,获得了SRAM器件的裂变谱中子单粒子翻转截面随特征尺寸变化的变化趋势。研究结果表明:SRAM器件的特征尺寸越小,其对低能中子导致的单粒子翻转的敏感性越高。     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型