非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET的解析模型

为抑制短沟道效应和热载流子效应, 提出了一种非对称HALO掺杂栅交叠轻掺杂漏围栅MOSFET新结构. 通过在圆柱坐标系中精确求解三段连续的泊松方程, 推导出新结构的沟道静电势、阈值电压以及亚阈值电流的解析模型. 结果表明, 新结构可有效抑制短沟道效应和热载流子效应, 并具有较小的关态电流. 此外, 分析还表明栅交叠区的掺杂浓度对器件的亚阈值电流几乎没有影响, 而栅电极功函数对亚阈值电流的影响较大. 解析模型结果和三维数值仿真工具ISE所得结果高度符合.     

Fluorine-plasma treated AlGaN/GaN high electronic mobility transistors under off-state overdrive stress

Influences of off-state overdrive stress on the fluorine-plasma treated AlGaN/GaN high-electronic mobility transistors (HEMTs) are experimentally investigated. It is observed that the reverse leakage current between the gate and source decreases after the off-state stress, whereas the current between the gate and drain increases. By analyzing those changes of the reverse currents based on the Frenkel-Poole model, we realize that the ionization of fluorine ions occurs during the off-state stress. Furthermore, threshold voltage degradation is also observed after the off-state stress, but the degradations of AlGaN/GaN HEMTs treated with different F-plasma RF powers are different. By comparing the differences between those devices, we find that the F-ions incorporated in the GaN buffer layer play an important role in averting degradation. Lastly, suggestions to obtain a more stable fluorine-plasma treated AlGaN/GaN HEMT are put forwarded.     

MOSFET scaling into the 10 nm regime

Scaling limits of the double-gate MOSFET structure are explored. Because short-channel effects can be adequately controlled by thinning the silicon body, the eventual scaling limit will be determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emission between the source and drain. Depending on threshold voltage and the source/drain doping profile, this will restrict gate length scaling to 5–11 nm. As power supplies are scaled down, maintaining on-state drive current may become difficult due to threshold voltage limitations. Series resistance becomes important as the body thickness is reduced, but intrinsic device performance may still be improved.     

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

A uniform doping ultra-thin silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor(LDMOS)with low specific on-resistance(R_on,sp) and high breakdown voltage(BV) is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate(AG) and back-side etching(BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping(VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.     

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

A new ultra-low specific on-resistance(Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor(VDMOS) with continuous electron accumulation(CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp.Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV).     

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage ($I_{\rm sub})$, gate-induced-drain-leakage ($I_{\rm GIDL})$, gate edge-direct-tunnelling leakage ($I_{\rm EDT})$ and band-to-band-tunnelling leakage ($I_{\rm BTBT})$ were analysed. For NMOS, $I_{\rm sub}$ can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.     

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors(NMOSFETs)is presented.In the process,a HfSiON gate dielectric with an equivalent oxide thickness of 10 A was prepared by a simple physical vapor deposition method.Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate.After the source/drain formation,the poly-Si dummy gate was removed by tetramethylammonium hydroxide(TMAH)wet-etching and replaced by a TaN metal gate.Because the metal gate was formed after the ion-implant doping activation process,the effects of the high temperature process on the metal gate were avoided.The fabricated device exhibits good electrical characteristics,including good driving ability and excellent sub-threshold characteristics.The device’s gate length is 73 nm,the driving current is 117μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μm.The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage(~0.24 V)for high performance NMOSFETs.The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.     

DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

A C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effects of the pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current (I_on), on/off current ratio (I_on/I_off), subthreshold swing (SS) transconductance (g_m), cut-off frequency (f_T) and gain-bandwidth product (GBP) are investigated. The optimized CSPTFET device exhibits excellent performance with high I_on (9.98×10 ^{- 4} A/μm), high I_on/I_off (～ 10¹¹), as well as low SS (～ 12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.     

绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

Quantum dot resonant tunneling FET on graphene

At this paper a field effect transistor based on graphene nanoribbon (GNR) is modeled. Like in most GNR-FETs the GNR is chosen to be semiconductor with a gap, through which the current passes at on state of the device. The regions at the two ends of GNR are highly n-type doped and play the role of metallic reservoirs so called source and drain contacts. Two dielectric layers are placed on top and bottom of the GNR and a metallic gate is located on its top above the channel region. At this paper it is assumed that the gate length is less than the channel length so that the two ends of the channel region are un-gated. As a result of this geometry, the two un-gated regions of channel act as quantum barriers between channel and the contacts. By applying gate voltage, discrete energy levels are generated in channel and resonant tunneling transport occurs via these levels. By solving the NEGF and 3D Poisson equations self consistently, we have obtained electron density, potential profile and current. The current variations with the gate voltage give rise to negative transconductance.     

A 20 nm gate-length ultra-thin body p-MOSFET with silicide source/drain

As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μ A μ m ^{− 1}on-current and on/off current ratios of 10⁶, for a conservative oxide thickness of 40 Å and | V_g − V_t| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in | V_t| is obtained in devices with gate lengths ranging from 100 to 20 nm.     

GaSb p-channel metal-oxide-semiconductor field-effect transistor and its temperature dependent characteristics

GaSb p-channel metal-oxide-semiconductor field-effect transistors(MOSFETs)with an atomic layer deposited Al2O3gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated.Temperature dependent electrical characteristics are investigated.Different electrical behaviors are observed in two temperature regions,and the underlying mechanisms are discussed.It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current,which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions.Methods to further reduce the off-state drain leakage current are given.     

0.18 μm MOSFET器件的总剂量辐照效应

对0.18 μm metal-oxide-semiconductor field-effect-transistor (MOSFET)器件进行γ射线辐照实验,讨论分析器件辐照前后关态漏电流、阈值电压、跨导、栅电流、亚阈值斜率等特性参数的变化,研究深亚微米器件的总剂量效应. 通过在隔离氧化物中引入等效陷阱电荷,三维模拟结果与实验结果符合很好. 深亚微米器件栅氧化层对总剂量辐照不敏感,浅沟槽隔离氧化物是导致器件性能退化的主要因素. 关键词： 总剂量效应 浅沟槽隔离 氧化层陷阱正电荷 MOSFET     

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

Si-doped zinc oxide(SZO) thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated.Moreover,the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure.The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm,and the optical band gap of the SZO film gradually increases with increasing Si content.The Si-doping can effectively suppress the grain growth of ZnO,revealed by atomic force microscope analysis.Compared with that of the undoped ZnO TFT,the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10~(-12) A,and thus the on/off current ratio is increased by more than two orders of magnitude.In summary,the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 10~6 and superior stability under gate-bias and drain-bias stress.     

Gate-tunable bandgap in bilayer graphene

The tight-binding model of bilayer graphene is used to find the gap between the conduction and valence bands as a function of both the gate voltage and the doping level by donors or acceptors. The total Hartree energy is minimized and an equation for the gap is obtained. This equation for the ratio of the gap to the chemical potential is determined only by the screening constant. Therefore, the gap is strictly proportional to the gate voltage or the carrier concentration in the absence of donors or acceptors. But in the case where the donors or acceptors are present, the gap demonstrates an asymmetric behavior on the electron and hole sides of the gate bias. A comparison with experimental data obtained by Kuzmenko et al. demonstrates a good agreement.     

22 nm工艺超薄体全耗尽绝缘体上硅晶体管单粒子瞬态效应研究

利用计算机辅助设计技术数值仿真工具, 研究22 nm工艺技术节点下超薄体全耗尽绝缘体上硅晶体管单粒子瞬态效应, 系统地分析了掺杂地平面技术、重离子入射位置、栅功函数和衬底偏置电压对于单粒子瞬态效应的影响. 模拟结果表明, 掺杂地平面和量子效应对于单粒子瞬态效应影响很小, 重离子入射产生大量电荷, 屏蔽了初始电荷分布的差异性. 单粒子瞬态效应以及收集电荷和重离子入射位置强相关, 超薄体全耗尽绝缘体上硅最敏感的区域靠近漏端. 当栅功函数从4.3 eV变化到4.65 eV时, 单粒子瞬态电流峰值从564 μA减小到509 μA, 收集电荷从4.57 fC减小到3.97 fC. 超薄体全耗尽绝缘体上硅器件单粒子瞬态电流峰值被衬底偏置电压强烈调制, 但是收集电荷却与衬底偏置电压弱相关. 关键词： 超薄体全耗尽绝缘体上硅 单粒子瞬态效应 电荷收集 数值仿真     

Off-state breakdown characteristics of InGaP-based high-barrier gate heterostructure field-effect transistors

In this work, the off-state breakdown characteristics of two different types InGaP-based high-barrier gate heterostructure field-effect transistors are studied and demonstrated. These devices have different high-barrier gate structures, e.g. the i-InGaP layer for device A and n  ⁺ - GaAs/p ⁺  -InGaP/n-GaAs camel-like structure for device B. The wide-gap InGaP layer is used to improve the breakdown characteristics. Experimentally, the studied devices show high off-state breakdown characteristics even at high temperature operation regime. This indicates that the studied devices are suitable for high-power and high-temperature applications. In addition, the off-state breakdown mechanisms are different for device A and B. For device A, off-state breakdown characteristics is only gate dominated at the temperature regime from 30 to 180  ^∘ C. For device B, off-state breakdown characteristics are gate and channel dominated at 30  ^∘ C and only gate dominated within 150 to 210  ^∘ C.     

Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

Low power fluorine plasma effects on electrical reliability of AlGaN/GaN high electron mobility transistor

The new electrical degradation phenomenon of the AlGaN/GaN high electron mobility transistor(HEMT) treated by low power fluorine plasma is discovered. The saturated current, on-resistance, threshold voltage, gate leakage and breakdown voltage show that each experiences a significant change in a short time stress, and then keeps unchangeable. The migration phenomenon of fluorine ions is further validated by the electron redistribution and breakdown voltage enhancement after off-state stress. These results suggest that the low power fluorine implant ion stays in an unstable state. It causes the electrical properties of AlGaN/GaN HEMT to present early degradation. A new migration and degradation mechanism of the low power fluorine implant ion under the off-stress electrical stress is proposed. The low power fluorine ions would drift at the beginning of the off-state stress, and then accumulate between gate and drain nearby the gate side. Due to the strong electronegativity of fluorine, the accumulation of the front fluorine ions would prevent the subsequent fluorine ions from drifting, thereby alleviating further the degradation of AlGaN/GaN HEMT electrical properties.     

Breakdown mechanisms in AlGaN/GaN high electron mobility transistors with different GaN channel thickness values

In this paper,the off-state breakdown characteristics of two different AlGaN/GaN high electron mobility transistors（HEMTs）,featuring a 50-nm and a 150-nm GaN thick channel layer,respectively,are compared.The HEMT with a thick channel exhibits a little larger pinch-off drain current but significantly enhanced off-state breakdown voltage(SV_off).Device simulation indicates that thickening the channel increases the drain-induced barrier lowering（DIBL） but reduces the lateral electric field in the channel and buffer underneath the gate.The increase of BV_off in the thick channel device is due to the reduction of the electric field.These results demonstrate that it is necessary to select an appropriate channel thickness to balance DIBL and BV_off in AlGaN/GaN HEMTs.