Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor (NMOS) transistor or P-channel metal-oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal-oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.     

Investigation of flux dependent sensitivity on single event effect in memory devices

Heavy-ion flux is an important experimental parameter in the ground based single event tests. The flux impact on a single event effect in different memory devices is analyzed by using GEANT4 and TCAD simulation methods. The transient radial track profile depends not only on the linear energy transfer(LET) of the incident ion, but also on the mass and energy of the ion. For the ions with the energies at the Bragg peaks, the radial charge distribution is wider when the ion LET is larger. The results extracted from the GEANT4 and TCAD simulations, together with detailed analysis of the device structure, are presented to demonstrate phenomena observed in the flux related experiment. The analysis shows that the flux effect conclusions drawn from the experiment are intrinsically connected and all indicate the mechanism that the flux effect stems from multiple ion-induced pulses functioning together and relies exquisitely on the specific response of the device.     

电离总剂量对纳米SRAM器件单粒子翻转敏感性的影响

电离总剂量（TID）与单粒子效应（SEE）是纳米SRAM器件在航天应用中的主要威胁。随着CMOS工艺的进步,两种辐射效应在纳米SRAM器件中的协同效应出现了一些新现象,有必要进一步开展深入研究。利用γ射线以及不同种类重离子对两款纳米SRAM器件开展了辐照实验,研究了不同辐照参数、测试模式以及数据图形条件下,电离总剂量对单粒子翻转（SEU）敏感性的影响。研究结果表明,γ射线辐照过后,存储单元中反相器开关阈值减小,漏电流增大,导致SRAM存储单元抗翻转能力降低,SEU截面有明显增大;未观察到"印记效应",数据图形对测试结果没有明显影响;多位翻转（MBU）比例无明显变化。     

Neutron-induced single event upset simulation in Geant4 for three-dimensional die-stacked SRAM

Three-dimensional integrated circuits(3D ICs)have entered into the mainstream due to their high performance,high integration,and low power consumption.When used in atmospheric environments,3D ICs are irradiated inevitably by neutrons.In this paper,a 3D die-stacked SRAM device is constructed based on a real planar SRAM device.Then,the single event upsets(SEUs)caused by neutrons with different energies are studied by the Monte Carlo method.The SEU cross-sections for each die and for the whole three-layer die-stacked SRAM device is obtained for neutrons with energy ranging from 1 MeV to 1000 MeV.The results indicate that the variation trend of the SEU cross-section for every single die and for the entire die-stacked device is consistent,but the specific values are different.The SEU cross-section is shown to be dependent on the threshold of linear energy transfer(LETth)and thickness of the sensitive volume(Tsv).The secondary particle distribution and energy deposition are analyzed,and the internal mechanism that is responsible for this difference is illustrated.Besides,the ratio and patterns of multiple bit upset(MBU)caused by neutrons with different energies are also presented.This work is helpful for the aerospace IC designers to understand the SEU mechanism of 3D ICs caused by neutrons irradiation.     

重离子辐照引起磁性隧道结功能失效类型及机理研究

重点研究了磁性隧道结(MTJ)的电学性能受离子注量影响的物理规律。实验首次发现了高能Ta离子辐射损伤导致MTJ电学功能失效的现象,主要失效模式为:高、低电阻态失效,其中79.9%的功能失效为高电阻态失效。计算表明,单个10.9 MeV/u的Ta离子辐照引入的损伤无法导致MTJ宏观电学功能失效。结合理论计算与Monte Carlo模拟分析,MTJ中的绝缘势垒层与铁磁薄膜的损伤是出现高、低电阻态失效的内因。