Oxygen Recovery in Hf Oxide Films Fabricated by Sputtering

The chemical structure of ultrathin Hf oxide films （〈 10 nm） fabricated by a standard sputtering method is investigated using x-ray spectroscopy and Rutherford backseattering spectroscopy. According to the experiments, oxygen species are impacted to the HfO2/Si interface during the initial sputtering, and then released back to the upper HfO2 region driven by the oxygen concentration grads. A vacuum annealing can greatly enhance this recovery process. Additionally, significant SiO2 reduction in the interface is observed after the vacuum annealing for the thick HfO2 films in our experiment. It might be an effective method to confine the interracial layer thickness by sputtering thick HfO2 in no-oxygen ambient.     

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance.     

Annealing Characteristics of ultra—thin high—K HfO2 gate dielectrics

Ultra-thin HfO2 gate-dielectric films were fabricated by ion-beam sputtering a sintered HfO2 target and subsequently annealed at different temperatures and atmospheres.We have studied the capacitance-voltage,current-voltage,and breakdon characteristics of the gate dielectrics.The results show that electrical characteristics of HfO2 gate dielectric are related to the annealing temperature.With increase annealing temperature,the largest value of capacitance decreases,the equivalent oxide thickness increases,the leakage current reduces,and the breakdown voltage decreases.     

Calculation of Specific Heat for Aluminium Thin Films

We employ Prasher＇s non-dimensional form to analyse the size effects on specific heat of Al thin films. Compared the calculation results of pure aluminium film with the experimental data, it is found that the reduction of phonon states is not the main reason of the size effect on the specific heat Al thin films with thickness from lOnm to 37Onm. However, the Al thin film in air usually has an oxidation layer and the specific heat of the layer is smaller than Al. By including the contribution of the oxidation layer to the thin-film specific heat, the calculation results are much closer to the experimental data. This may be a possible reason of the size effects on specific heat of Al thin films.     

Transition of Magnetoresistance in Co/Alq3 Granular Film on Silicon Substrate

A Coo.3s （Alq3）o.62 granular film is prepared using a co-evaporating technique on a silicon substrate with a native oxide layer. A crossover of magnetoresistance （MR） from positive to negative is observed. The positive MR ratio reaches 17.5% at room temperature （H = 50kOe）, and the negative MR ratio reaches -1.35% at 1514 （H = 10 kOe）. Furthermore, a metal-insulator transition is also observed. The transition of resistance and MR results from the channel switching of electron transport between the upper Co-AIq3 granular film and the inversion layer underneath. The negative MR originates from the tunneling magnetoresistance effect due to the tunneling conducting between adjacent Co granules, and the positive MR may be attributed to the transport of high mobility carriers in the SiO2/Si inversion layer.     

Discrete Charge Storage Nonvolatile Memory Based on Si Nanocrystals with Nitridation Treatment

A nonvolatile memory device with nitrided Si nanocrystals embedded in a floating gate was fabricated. The uniform Si nanocrystals with high density （3× 10^11 cm^-2 ） were deposited on ultra-thin tunnel oxide layer （- 3 nm） and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanoerystals, which slows the charge loss rate.     

Electrical properties and reliability of HfO2 gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

Trichloroethylene （TCE） pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties, gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growths the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and HC1 on the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.     

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide(NO) annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor(MOS) devices has been investigated using the time-dependent bias stress(TDBS),capacitance–voltage(C–V),and secondary ion mass spectroscopy(SIMS).It is revealed that two main categories of charge traps,near interface oxide traps(Nniot) and oxide traps(Not),have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.     

Analysis of flatband voltage shift of metal/high-k/SiO2/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage(VFB) of metal/high-k/SiO2/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFBis obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFBof TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results.Furthermore, both positive VFBshift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.     

Determination of Tungsten Layer Profiles in Bilayer Structures Using X-Ray Reflectivity Method

An effectual method is presented to determine the profiles of a tungsten （W） layer, such as the density, the thickness and the roughness in the multilayer structures, using the x-ray reflectivity technique. To avoid oxidation effects of tungsten, a B4 C capping layer is deposited onto to the W layer. To observe the profiles of the tungsten layer with different thicknesses, three groups of W/B4 C bilayers with different thicknesses are prepared by using ultra high vacuum dc magnetron sputtering and measured by an x-ray diffractometer. A type of genetic algorithm called the differential evolution is used to simulate the measurement data so as to obtain the parameters of bilayers. According to the simulation, it is shown that the W layer density varies from 95.26% to 97.51% compared to the bulk. In our experiment, the deposition rate is 0.044 nm/s, and the thickness is varied in the range of 9.8-19.4 nm.     

Oxidation of silicon surface with atomic oxygen radical anions

The surface oxidation of silicon （Si） wafers by atomic oxygen radical anions （O- anions） and the preparation of metal-oxide-semiconductor （MOS） capacitors on the O-oxidized Si substrates have been examined for the first time. The O- anions are generated from a recently developed O- storage-emission material of [Ca24Al2sO64]^4＋·4O^- （Cl2A7-O^- for short）. After it has been irradiated by an O- anion bean： （0.5 μA/cm^2） at 300℃ for 1-10 hours, the Si wafer achieves an oxide layer with a thickness ranging from 8 to 32 nm. X-ray photoelectron spectroscopy （XPS） results reveal that the oxide layer is of a mixture of SiO2, Si2 O3, and Si2O distributed in different oxidation depths. The features of the MOS capacitor of 〈Al electrode/SiOx/Si〉 are investigated by measuring capacitance-voltage （C - V） and current-voltage （I - V） curves. The oxide charge density is about 6.0 × 10^1 cm^-2 derived from the （C - V curves. The leakage current density is in the order of 10^-6 A/cm^2 below 4 MV/cm, obtained from the I - V curves. The O- anions formed by present method would have potential applications to the oxidation and the surface-modification of materials together with the preparation of semiconductor devices.     

Analysis of flatband voltage shift of metallhigh-k/Si02/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.     

Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

In this paper,we investigate the performance of the bulk fin field effect transistor(FinFET) through a threedimensional(3D) full band Monte Carlo simulator with quantum correction.Several scattering mechanisms,such as the acoustic and optical phonon scattering,the ionized impurity scattering,the impact ionization scattering and the surface roughness scattering are considered in our simulator.The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work.Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.     

Influences of Pressure and Substrate Temperature on Epitaxial Growth of γ-Mg2SiO4 Thin Films on Si Substrates

An epitsucial γ-Mg2SiO4 thin film can be a good buffer between the Si substrate and some oxide thin films. For high temperature superconducting multilayer structures, hopefully it can be taken as an insulating layer to replace the widely used MgO film. To explore such possibilities, we carry out systematic studies on the influences of pressure and substrate temperature on the epitaxy of γ-Mg2SiO4 thin films grown on Si （100） substrates using rf magnetron sputtering with an Mg target of purity of 99.95 percent. With the substrate temperature kept at 500℃ and the pressure changing from lO Pa to 15 Pa, in the XRD spectra the 7-Mg2SiO4 （400） peak grows drastically while the MgO （200） peak is suppressed. Keeping the pressure at 15Pa and increasing the temperature from 500℃ to 570℃ further can improve the film epitaxy, while working at 780℃ and 11Pa seems to give very good results. X-ray photoelectronic spectroscopy and φ scan are used to characterize the stoichiometry, crystallinity, and in-plane growth of the samples.     

Wet thermal annealing effect on TaN/HfO2/Ge metal-oxide-semiconductor capacitors with and without a GeO2 passivation layer

Wet thermal annealing effects on the properties of TaN/HfO2/Ge metal-oxide-semiconductor(MOS) structures with and without a GeO2 passivation layer are investigated.The physical and the electrical properties are characterized by X-ray photoemission spectroscopy,high-resolution transmission electron microscopy,capacitance-voltage(C-V) and current-voltage characteristics.It is demonstrated that wet thermal annealing at relatively higher temperature such as 550℃ can lead to Ge incorporation in HfO2 and the partial crystallization of HfO2,which should be responsible for the serious degradation of the electrical characteristics of the TaN/HfO2/Ge MOS capacitors.However,wet thermal annealing at 400℃ can decrease the GeO x interlayer thickness at the HfO2/Ge interface,resulting in a significant reduction of the interface states and a smaller effective oxide thickness,along with the introduction of a positive charge in the dielectrics due to the hydrolyzable property of GeO x in the wet ambient.The pre-growth of a thin GeO2 passivation layer can effectively suppress the interface states and improve the C-V characteristics for the as-prepared HfO2 gated Ge MOS capacitors,but it also dissembles the benefits of wet thermal annealing to a certain extent.     

A novel trilayer antireflection coating using dip-coating technique

We report a new structure for broadband antireflection coating by dip-coating technique, which has minimal cost and is compatible with large-scale manufacturing. The coatings are prepared by depositing SiO 2 sol-gel film on a glass substrate, subsequently depositing SiO 2 single-layer particle coating through electrostatic attraction, and depositing a final very thin SiO 2 sol-gel film to improve the mechanical strength of the whole coating structure. The refractive index of the structure changes gradually from the top to the substrate. The transmittance of a glass substrate has been experimentally found to be improved in the spectral range of 400 1 400 nm and in the incidence angle range from 0 to at least 45 . The mechanical strength is immensely improved because of the additional thin SiO 2 sol-gel layer. The surface texture can be applied to the substrates of different materials and shapes as an add-on coating.     

Numerical study of laser-induced collision process in Eu-Sr in strong field

Theoretically based on the four-level model, one LICET process in Eu-Sr system in both weak and strong fields was calculated by immediate numerical integrations. Numerical results in weak field are in fair to good agreement with analytical ones. Numerical results in strong field show that: (a) the peak of the LICET profiles moves to the violet side and the tuning range of the profiles obviously becomes narrower when the laser field intensity increases; and (b) numerical results in strong field differ a lot from analytical ones, which indicates that in strong field, the analytical expressions are not applicable any longer.     

Cap Layer Influence on Impurity-Free Vacancy Disordering of InGaAs/InP Quantum Well Structure

Quantum well intermixing （QWI） by the impurity-free vacancy disordering （IFVD） technique is an important and effective approach for the monolithic integration of optoelectronic devices based on InGaAs/InP quantum well structures. We experimentally investigate the influence of the capping layer SiO2 and Si3N4 on the QWI by IFVD. The results show that for all the samples with three-types differently doped （P, N and I） top InP layers, Si3N4 can always induce a larger photoluminescence blueshift than SiO2 in the IFVD QWI process, which attributes more to the group III and V vacancies point defects created in the interface of Si3N4-InP than that of SiO2-InP, proved by the SIMS measurements. The inherent mechanisms for explaining these properties are further discussed.     

improvement of electrical properties of Cu/SiCOH low-k film integrated system by O2 plasma treatment

This paper investigates the effect of O2 plasma treatment on the electric property of Cu/SiCOH low dielectric constant （low-k） film integrated structure. The results show that the leakage current of Cu/SiCOH low-k integrated structure can be reduced obviously at the expense of a slight increase in dielectric constant k of SiCOH films. Bythe Fourier transform infrared （FTIR） analysis on the bonding configurations of SiCOH films treated by O2 plasmar it is found that the decrease of leakage current is related to the increase of Si-O cages originating from the linkage of Si dangling bonds through O, which makes the open pores sealed and reduces the diffusion of Cu to pores.     

Device topological thermal management of β-Ga_2O_3 Schottky barrier diodes

The ultra-wide bandgap semiconductor β gallium oxide(β-Ga_2 O_3) gives promise to low conduction loss and high power for electronic devices. However, due to the natural poor thermal conductivity of β-Ga_2 O_3, their power devices suffer from serious self-heating effect. To overcome this problem, we emphasize on the effect of device structure on peak temperature in β-Ga_2 O_3 Schottky barrier diodes(SBDs) using TCAD simulation and experiment. The SBD topologies including crystal orientation of β-Ga_2 O_3, work function of Schottky metal, anode area, and thickness, were simulated in TCAD, showing that the thickness of β-Ga_2 O_3 plays a key role in reducing the peak temperature of diodes. Hence, we fabricated β-Ga_2 O_3 SBDs with three different thickness epitaxial layers and five different thickness substrates. The surface temperature of the diodes was measured using an infrared thermal imaging camera. The experimental results are consistent with the simulation results. Thus, our results provide a new thermal management strategy for high power β-Ga_2 O_3 diode.