多晶SiGe栅量子阱pMOSFET阈值电压模型

本文基于多晶SiGe栅量子阱SiGe pMOSFET器件物理,考虑沟道反型时自由载流子对器件纵向电势的影响,通过求解泊松方程,建立了p+多晶SiGe栅量子阱沟道pMOS阈值电压和表面寄生沟道开启电压模型.应用MATLAB对该器件模型进行了数值分析,讨论了多晶Si_1-yGe_y栅Ge组分、Si_1-xGe_x量子阱沟道Ge组分、栅氧化层厚度、Si帽层厚度、沟道区掺杂浓度和 关键词： 多晶SiGe栅 寄生沟道 量子阱沟道 阈值电压     

Plasma immersion ion implantation with dielectric substrates

Plasma immersion ion implantation (PIII) is a novel implantation technique for high-dose/high-current implants. Using the SPICE circuit simulator to model the PIII process, the sheath voltage and ion energy distribution are examined. Implanting into a dielectric substrate results in a significant voltage buildup in the wafer, reducing the effective implant energy. Increasing the pulse voltage raises the dose/pulse, but at the cost of an expanded implant energy spread. Increasing the plasma ion density also raises the dose/pulse, but at the cost of a wider implant energy spread and a lower coupling efficiency. Increasing the substrate thickness reduces both the coupling efficiency and dose/pulse while broadening the energy spread. The large voltage generated across the dielectric substrate decreases the charge neutralization time significantly, reducing the possibility of gate oxide damage     

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure

The threshold voltage (V_th) of the p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated via Silvaco-Atlas simulations. The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier height Φ_1,p, polarization charge density σ_b, and equivalent unite capacitance C_oc. It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V_th, and threshold voltage |V_th| increases with the reduction in p-GaN doping concentration and the work-function of gate metal. Meanwhile, the increase in gate dielectric relative permittivity may cause the increase in threshold voltage |V_th|. Additionally, the parameter influencing output current most is the p-GaN doping concentration, and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5×10¹⁶ cm^-3 at V_GS = -12 V and V_DS = -10 V.     

65 nm互补金属氧化物半导体场效应和晶体管总剂量效应及损伤机制

对65 nm互补金属氧化物半导体工艺下不同尺寸的N型和P型金属氧化物半导体场效应晶体管(NMOSFET和PMOSFET)开展了不同偏置条件下电离总剂量辐照实验.结果表明:PMOSFET的电离辐射响应与器件结构和偏置条件均有很强的依赖性,而NMOSFET表现出较强的抗总剂量性能;在累积相同总剂量时,PMOSFET的辐照损伤远大于NMOSFET.结合理论分析和数值模拟给出了PMOSFET的辐射敏感位置及辐射损伤的物理机制.     

同步对称双栅InGaZnO薄膜晶体管电势模型研究

研究了同步对称双栅氧化铟镓锌薄膜晶体管(InGaZnO thin film transistors,IGZO TFTs)的沟道电势,利用表面电势边界方程联合Lambert函数推导得到了器件沟道电势的解析模型.该模型考虑了IGZO薄膜中存在深能态及带尾态等缺陷态密度,能够同时精确地描述器件在亚阈区(sub-threshold)与开启区(above threshold)的电势分布.基于所提出的双栅IGZO TFT模型,讨论了不同厚度的栅介质层和有源层时,栅-源电压对双栅IGZO TFT的表面势以及中心势的调制效应.对比分析了该模型的计算值与数值模拟值,结果表明二者具有较高的符合程度.     

γ射线总剂量辐照对单轴应变Si纳米n型金属氧化物半导体场效应晶体管栅隧穿电流的影响

基于γ射线辐照条件下单轴应变Si纳米n型金属氧化物半导体场效应晶体管(NMOSFET)载流子的微观输运机制,揭示了单轴应变Si纳米NMOSFET器件电学特性随总剂量辐照的变化规律,同时基于量子机制建立了小尺寸单轴应变Si NMOSFET在γ射线辐照条件下的栅隧穿电流模型,应用Matlab对该模型进行了数值模拟仿真,探究了总剂量、器件几何结构参数、材料物理参数等对栅隧穿电流的影响.此外,通过实验进行对比,该模型仿真结果和总剂量辐照实验测试结果基本符合,从而验证了模型的可行性.本文所建模型为研究纳米级单轴应变Si NMOSFET应变集成器件可靠性及电路的应用提供了有价值的理论指导与实践基础.     

基于原位等离子体氮化及低压化学气相沉积-Si_3N_4栅介质的高性能AlGaN/GaN MIS-HEMTs器件的研究

通过对低压化学气相沉积(LPCVD)系统进行改造,实现在沉积Si_3N_4薄膜前的原位等离子体氮化处理,氮等离子体可以有效地降低器件界面处的氧含量和悬挂键,从而获得了较低的LPCVD-Si_3N_4/GaN界面态,通过这种技术制作的MIS-HEMTs器件,在扫描栅压范围V_(G-sweep)=(-30 V,+24 V)时,阈值回滞为186 mV,据我们所知为目前高扫描栅压V_(G+)(20 V)下的最好结果.动态测试表明,在400 V关态应力下,器件的导通电阻仅仅上升1.36倍(关态到开态的时间间隔为100μs).     

Two-dimensional modeling of a micro-cell plasma in Xe driven byhigh frequency

Two-dimensional simulation of a micro-cell plasma driven by high frequency at 13.56 MHz is described in Xe. The minimum sustaining voltage (V_s)_min in an ideal infinite parallel plates at high frequency is first discussed as a function of both pd and fd (f the applied frequency, d the electrode distance, and p the gas pressure). As decreasing d,(V_s)_min increases at fixed f, while (V_s)_min decreases with increasing fd at fixed pd in a high frequency discharge under the condition of a spatial ion trapping. A capability for maintaining a micro-cell plasma is investigated under fd<υ(d_e)/π for different two-dimensional geometry of the micro cell (υ(d_e) is the effective drift velocity of electrons). The influence of the secondary electron from the electrode becomes important for the maintenance of a microcell plasma and emission efficiency. A powered ring electrode and ground plate system realizes the micro-cell plasma with high density at 13.56 MHz     

部分耗尽结构绝缘体上硅器件的低频噪声特性

针对部分耗尽结构绝缘体上硅(silicon-on-insulator, SOI)器件低频噪声特性展开实验与理论研究. 实验结果表明, 器件低频噪声主要来源于SiO₂-Si界面附近缺陷态对载流子的俘获与释放过程; 基于此理论可提取前栅和背栅氧化层界面附近缺陷态密度分别为8×10¹⁷ eV^-1·cm^-3和2.76×10¹⁷ eV^-1·cm^-3. 基于电荷隧穿机理, 在考虑隧穿削弱因子、隧穿距离与时间常数之间关系的基础上, 提取了前、背栅氧化层内缺陷态密度随空间的分布情况. 此外, SOI器件沟道电流归一化噪声功率谱密度随沟道长度的增加而线性减小, 这表明器件低频噪声主要来源于沟道的闪烁噪声. 最后, 基于电荷耦合效应, 分析了背栅电压对前栅阈值电压、沟道电流以及沟道电流噪声功率谱密度的影响.     

单晶金刚石氢终端场效应晶体管特性

基于微波等离子体化学气相淀积生长的单晶金刚石制作了栅长为2μm的耗尽型氢终端金刚石场效应晶体管,并对器件特性进行了分析.器件的饱和漏电流在栅压为-6 V时达到了96 mA/mm,但是在-6 V时栅泄漏电流过大.在-3.5 V的安全工作栅压下,饱和漏电流达到了77 mA/mm.在器件的饱和区,宽5.9 V的栅电压范围内,跨导随着栅电压的增加而近线性增大到30 mS/mm.通过对器件导通电阻和电容-电压特性的分析,氢终端单晶金刚石的二维空穴气浓度达到了1.99×10~(13)cm~(-2),并且迁移率和载流子浓度均随着栅压向正偏方向的移动而逐渐增大.分析认为,沟道中高密度的载流子、大的栅电容以及迁移率的逐渐增加是引起跨导在很大的栅压范围内近线性增加的原因.     

InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究

本文通过解析阵列基板栅极驱动(gate driver on array, GOA)电路中发生静电释放(electro-static discharge,ESD)的InGaZnO薄膜晶体管(InGaZnO thin-film transistor, IGZO TFT)器件发现:栅极Cu金属扩散进入了SiN_x/SiO_2栅极绝缘层;源漏极金属层成膜前就发生了ESD破坏;距离ESD破坏区域越近的IGZO TFT,电流开关比越小,直到源漏极与栅极完全短路.本文综合IGZO TFT器件工艺、GOA区与显示区金属密度比、栅极金属层与绝缘层厚度非均匀性分布等因素,采用ESD器件级分析与系统级分析相结合的方法,提出栅极Cu:SiN_x/SiO_2界面缺陷以及这三层薄膜的厚度非均匀分布是导致GOA电路中沟道宽长比大的IGZO TFT发生ESD失效的关键因素,并针对性地提出了改善方案.     

0.18μm CMOS工艺栅极氧化膜可靠性的衬底和工艺依存性

用斜坡电压法(Voltage Ramp, V-ramp)评价了0.18μm双栅极 CMOS工艺栅极氧化膜击穿电量(Charge to Breakdown, Q_bd)和击穿电压(Voltage to Breakdown, V_bd). 研究结果表明，低压器件(1.8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小，而高压器件(3.3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大，击穿电压测试值也发现与击穿电量 关键词： 薄氧 可靠性 击穿电压 击穿电量     

Valence band electron tunneling in metal-oxide-silicon structures

Experimental results are presented for the substrate current appearing in thin oxide metal-oxide-silicon capacitors with a shallow n/p junction beneath the gate when a positive gate voltage in the tunneling regime is applied. The analysis of the current-voltage characteristics shows that for an oxide voltage drop lower than about 5 V the substrate current is due to electron tunneling from the silicon valence band. The dispersion relation in the energy range extending 3 eV below the oxide conduction band is determined from the voltage dependence of the current in the direct tunneling regime. An effective mass of about 0.8m_e is found near the edge of the oxide conduction band, while for lower energies a strong decrease of the effective mass is observed.     

Low voltage substrate current： a monitor for interface states generation in ultra-thin oxide n-MOSFETs under constant voltage stresses

The low voltage substrate current （Ib） has been studied based on generation kinetics and used as a monitor of interface states （Nit） generation for ultra-thin oxide n-MOSFETs under constant voltage stress. It is found that the low voltage Ib is formed by electrons tunnelling through interface states, and the variations of Ib（△Ib） are proportional to variations of Nit （△Nit）. The Nit energy distributions were determined by differentiating Nit（Vg）. The results have been compared with that measured by using gate diode technique.[第一段]     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

Study on a novel vertical enhancement-mode Ga2O3 MOSFET with FINFET structure

A novel enhanced mode(E-mode)Ga₂O₃ metal-oxide-semiconductor field-effect transistor(MOSFET)with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated.It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics.The metal material of the gate,the oxide material,the oxide thickness,and the epitaxial layer concentration strongly affect the threshold voltage and the output currents.Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant.When the output current density of the device increases,the source concentration,the thickness of the epitaxial layer,and the total width of the device need to be expanded.The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage.It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga₂O₃ MOSFET requires the epitaxial layer concentration,the channel height of the device,the thickness of the source region,and the oxide thickness of the device should be less than 5×10¹⁶ cm^-3,less than 1.5μm,between 0.1μm-0.3μm and less than 0.08μm,respectively.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

介质中双缺陷电荷对碳纳米管场效应晶体管量子输运特性的影响

用非平衡格林函数理论和紧束缚模型近似计算长沟道弹道输运p型碳纳米管场效应管中电流强度.研究当场效应管介质（SiO₂）中存在两个带电缺陷时，载流子散射所引起的电流强度减小和栅极阈值电压偏移量与缺陷位置的关系.介质中两个缺陷所带电荷Q₁=Q₂=+e（-e为电子电荷），都靠近源极或者都靠近漏极，或者一个电荷靠近源极另一个电荷靠近漏极.在工作状态下，所引起的电流强度相对减小比介质中只存在单个正电荷Q=+e且靠近源极（或漏极）时所引起的电流强度相对减小大得多.如果两个正电荷都在沟道中央附近，随着两个电荷的轴向距离减小，栅极阈值电压偏移的绝对值明显增加.栅极阈值电压偏移可达到-0.35 V.     

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.     

埋氧注氮工艺对部分耗尽SOI PMOSFET顶栅氧的辐射硬度的影响

研究了埋氧注氮对部分耗尽SOI PMOSFET顶栅氧的总剂量辐射硬度所造成的影响。注入埋氧的氮剂量分别是8×1015 , 2×1016 和1×1017cm-2。实验结果表明，辐照前，晶体管的阈值电压随氮注入剂量的增加向负方向漂移。在正2V的栅偏压下，经5×105 rad(Si)的总剂量辐照后，同埋氧未注氮的晶体管相比，埋氧注氮剂量为8×1015 cm-2的晶体管呈现出了较小的阈值电压漂移量。然而，当注氮剂量高达2×1016 和 1×1017cm-2时，所测大多数晶体管的顶栅氧却由于5×105 rad(Si)的总剂量辐照而受到了严重损伤。另外，对于顶栅氧严重受损的晶体管，其体-漏结也受到了损伤。所有的实验结果可通过氮注入过程中对顶硅的晶格损伤来解释。