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InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究
引用本文:马群刚,周刘飞,喻玥,马国永,张盛东.InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究[J].物理学报,2019,68(10):108501-108501.
作者姓名:马群刚  周刘飞  喻玥  马国永  张盛东
作者单位:1. 北京大学信息工程学院, 深圳 518055; 2. 北京大学信息科学技术学院, 北京 100871; 3. 南京中电熊猫平板显示科技有限公司, 南京 210033
摘    要:本文通过解析阵列基板栅极驱动(gate driver on array, GOA)电路中发生静电释放(electro-static discharge,ESD)的InGaZnO薄膜晶体管(InGaZnO thin-film transistor, IGZO TFT)器件发现:栅极Cu金属扩散进入了SiN_x/SiO_2栅极绝缘层;源漏极金属层成膜前就发生了ESD破坏;距离ESD破坏区域越近的IGZO TFT,电流开关比越小,直到源漏极与栅极完全短路.本文综合IGZO TFT器件工艺、GOA区与显示区金属密度比、栅极金属层与绝缘层厚度非均匀性分布等因素,采用ESD器件级分析与系统级分析相结合的方法,提出栅极Cu:SiN_x/SiO_2界面缺陷以及这三层薄膜的厚度非均匀分布是导致GOA电路中沟道宽长比大的IGZO TFT发生ESD失效的关键因素,并针对性地提出了改善方案.

关 键 词:Cu互连  InGaZnO薄膜晶体管  阵列基板栅极驱动  静电释放
收稿时间:2019-02-27

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane
Ma Qun-Gang,Zhou Liu-Fei,Yu Yue,Ma Guo-Yong,Zhang Sheng-Dong.Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane[J].Acta Physica Sinica,2019,68(10):108501-108501.
Authors:Ma Qun-Gang  Zhou Liu-Fei  Yu Yue  Ma Guo-Yong  Zhang Sheng-Dong
Institution:1. School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, China; 2. School of Electronics Engineering and Computer Science, Peking University, Beijing 100871, China; 3. Nanjing CEC Panda FPD Technology Co., Ltd., Nanjing 210033, China
Abstract:There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiNx/SiO2 insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiNx/SiO2. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (Vth) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(W/L) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiNx/SiO2 leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiNx film and SiO2 film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure.
Keywords:Cu interconnect  electrostatic-discharge  InGaZnO thin film transistor  gate driver on array
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