| Impact of STI indium implantation on reliability of gate oxide |
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| 作者姓名： | 陈晓亮 陈天 孙伟锋 钱忠健 李玉岱 金兴成 |
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| 作者单位： | 1.National ASIC System Engineering Research Center, School of Electronic Science & Engineering, Southeast University, Nanjing 210096, China;2.China Resources Microelectronics Co., Ltd, China |
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| 摘 要： | The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.
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| 关 键 词： | SILICON-ON-INSULATOR shallow trench isolation(STI)implantation gate oxide reliability |
| 收稿时间： | 2021-05-20 |
Impact of STI indium implantation on reliability of gate oxide |
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| Xiao-Liang Chen,Tian Chen,Wei-Feng Sun,Zhong-Jian Qian,Yu-Dai Li,Xing-Cheng Jin.Impact of STI indium implantation on reliability of gate oxide[J].Chinese Physics B,2022,31(2):28505-028505. |
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| Authors: | Xiao-Liang Chen Tian Chen Wei-Feng Sun Zhong-Jian Qian Yu-Dai Li Xing-Cheng Jin |
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| Affiliation: | 1.National ASIC System Engineering Research Center, School of Electronic Science & Engineering, Southeast University, Nanjing 210096, China;2.China Resources Microelectronics Co., Ltd, China |
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| Abstract: | The impacts of shallow trench isolation (STI) indium implantation on gate oxide and device characteristics are studied in this work. The stress modulation effect is confirmed in this research work. An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress, and the thickness gap is around 5%. Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator (SOI) process. The ramped voltage stress and time to breakdown capability of the gate oxide are researched. No early failure is observed for both wafers the first time the voltage is ramped up. However, a time dependent dielectric breakdown (TDDB) test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation. Meanwhile, the device characteristics are compared, and the difference between two devices is consistent with the equivalent oxide thickness (EOT) gap. |
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| Keywords: | silicon-on-insulator shallow trench isolation (STI) implantation gate oxide reliability |
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