绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

0.18μm CMOS工艺栅极氧化膜可靠性的衬底和工艺依存性

用斜坡电压法(Voltage Ramp, V-ramp)评价了0.18μm双栅极 CMOS工艺栅极氧化膜击穿电量(Charge to Breakdown, Q_bd)和击穿电压(Voltage to Breakdown, V_bd). 研究结果表明，低压器件(1.8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小，而高压器件(3.3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大，击穿电压测试值也发现与击穿电量 关键词： 薄氧 可靠性 击穿电压 击穿电量     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

Study on a novel vertical enhancement-mode Ga2O3 MOSFET with FINFET structure

A novel enhanced mode(E-mode)Ga₂O₃ metal-oxide-semiconductor field-effect transistor(MOSFET)with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated.It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics.The metal material of the gate,the oxide material,the oxide thickness,and the epitaxial layer concentration strongly affect the threshold voltage and the output currents.Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant.When the output current density of the device increases,the source concentration,the thickness of the epitaxial layer,and the total width of the device need to be expanded.The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage.It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga₂O₃ MOSFET requires the epitaxial layer concentration,the channel height of the device,the thickness of the source region,and the oxide thickness of the device should be less than 5×10¹⁶ cm^-3,less than 1.5μm,between 0.1μm-0.3μm and less than 0.08μm,respectively.     

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT)stresses are studied using NMOSFET with 1.4- nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.     

电压应力下超薄栅氧化层n-MOSFET的击穿特性

研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性，包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性，分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透.在电压应力下，SiO₂中形成的缺陷不仅降低了SiO₂的势垒高度，而且等效减小了SiO₂的厚度(势垒宽度).另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长. 关键词： 超薄栅氧化层 斜坡电压 经时击穿 渗透     

用反应溅射法沉积SiO_x绝缘层的InGaZnO-TFT的光照稳定性(英文)

制备了基于反应溅射SiOx绝缘层的InGaZnO-TFT,并系统地研究了InGaZnO-TFT在白光照射下的稳定性,主要涉及到光照、负偏压、正偏压、光照负偏压和光照正偏压5种情况。结果表明,器件在光照和负偏压光照下的阈值偏移较大,而在正偏压光照情况下的阈值偏移几乎可以忽略。采用C-V方法证明阈值电压漂移是源于绝缘层/有源层附近及界面处的缺陷。另外,采用指数模式计算了缺陷态的弛豫时间。本研究的目的就是揭示InGaZnO-TFT在白光照射和偏压下的不稳定的原因。     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

Multifunctional silicon-based light emitting device in standard complementary metal–oxide–semiconductor technology

A three-terminal silicon-based light emitting device is proposed and fabricated in standard 0.35 μ m complementary metal--oxide--semiconductor technology. This device is capable of versatile working modes: it can emit visible to near infra-red (NIR) light (the spectrum ranges from 500 nm to 1000 nm) in reverse bias avalanche breakdown mode with working voltage between 8.35 V--12 V and emit NIR light (the spectrum ranges from 900 nm to 1300 nm) in the forward injection mode with working voltage below 2 V. An apparent modulation effect on the light intensity from the polysilicon gate is observed in the forward injection mode. Furthermore, when the gate oxide is broken down, NIR light is emitted from the polysilicon/oxide/silicon structure. Optoelectronic characteristics of the device working in different modes are measured and compared. The mechanisms behind these different emissions are explored.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction (SJ) MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.     

电荷耦合效应对高耐压沟槽栅极超势垒整流器击穿电压的影响

通过沟槽结构和可调节的电子势垒,沟槽栅极超势垒整流器可以更为有效地实现通态压降和反向漏电流之间的良好折衷.在高压应用时,电荷耦合效应对于提高该器件的反向承压能力起到了关键作用.本文通过理论模型与器件模拟结果,分析了沟槽深度、栅氧厚度和台面宽度等关键参数对电荷耦合作用下二维电场分布的影响,归纳出了提高该器件击穿电压的思路与方法,为器件设计提供了有意义的指导.在此基础上,提出了阶梯栅氧结构,该结构在维持几乎相同击穿电压的同时,使正向导通压降降低51.49%.     

薄栅氧化层经时击穿的参数表征研究

在恒压应力条件下测试了薄栅氧化层的击穿特性,研究了TDDB的击穿机理,讨论了栅氧化层面积对击穿特性的影响.对击穿电荷Q_BD进行了实验测试和分析,结果表明：击穿电荷Q_BD不是常数,它依赖栅氧化层面积和栅电压.对相关系数进行了拟合,给出了Q_BD的解析表达式. 关键词：     

Annealing Characteristics of ultra—thin high—K HfO2 gate dielectrics

Ultra-thin HfO2 gate-dielectric films were fabricated by ion-beam sputtering a sintered HfO2 target and subsequently annealed at different temperatures and atmospheres.We have studied the capacitance-voltage,current-voltage,and breakdon characteristics of the gate dielectrics.The results show that electrical characteristics of HfO2 gate dielectric are related to the annealing temperature.With increase annealing temperature,the largest value of capacitance decreases,the equivalent oxide thickness increases,the leakage current reduces,and the breakdown voltage decreases.     

Impact of substrate bias on radiation-induced edge effects in MOSFETs

This paper investigates the effects of gamma-ray irradiation on the Shallow-Trench Isolation (STI) leakage currents in 180-nm complementary metal oxide semiconductor technology. No hump effect in the subthreshold region is observed after irradiation, which is considered to be due to the thin STI corner oxide thickness. A negative substrate bias could effectively suppress the STI leakage, but it also impairs the device characteristics. The three-dimensional simulation is introduced to understand the impact of substrate bias. Moreover, we propose a simple method for extracting the best substrate bias value, which not only eliminates the STI leakage but also has the least impact on the device characteristics.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

A 3D SiC MOSFET with poly-silicon/SiC heterojunction diode

A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively.     

Breakdown mechanisms in AlGaN/GaN high electron mobility transistors with different GaN channel thickness values

In this paper,the off-state breakdown characteristics of two different AlGaN/GaN high electron mobility transistors（HEMTs）,featuring a 50-nm and a 150-nm GaN thick channel layer,respectively,are compared.The HEMT with a thick channel exhibits a little larger pinch-off drain current but significantly enhanced off-state breakdown voltage(SV_off).Device simulation indicates that thickening the channel increases the drain-induced barrier lowering（DIBL） but reduces the lateral electric field in the channel and buffer underneath the gate.The increase of BV_off in the thick channel device is due to the reduction of the electric field.These results demonstrate that it is necessary to select an appropriate channel thickness to balance DIBL and BV_off in AlGaN/GaN HEMTs.     

Operational improvement of AlGaN/GaN HEMT on SiC substrate with the amended depletion region

In this paper, a high performance AlGaN/GaN High Electron Mobility Transistor (HEMT) on SiC substrates is presented to improve the electrical operation with the amended depletion region using a multiple recessed gate (MRG–HEMT). The basic idea is to change the gate depletion region and a better distribution of the electric field in the channel and improve the device breakdown voltage. The proposed gate consists of lower and upper gate to control the channel thickness. Also, the charge of the depletion region will change due to the optimized gate. In addition, a metal between the gate and drain including the horizontal and vertical parts is used to better control the thickness of the channel. The breakdown voltage, maximum output power density, cut-off frequency, maximum oscillation frequency, minimum noise figure, maximum available gain (MAG), and maximum stable gain (MSG) are some parameters for designers which are considered and are improved in this paper.     

The degradation and recovery properties of AlGaN/GaN high-electron mobility transistors under direct current reverse step voltage stress

Direct current(DC) reverse step voltage stress is applied on the gate of an AlGaN/GaN high-electron mobility transistor(HEMT).Experiments show that parameters degenerate under stress.Large-signal parasitic source/drain resistance(RS/RD) and gate-source forward I-V characteristics are recoverable after breakdown of the device under test(DUT).Electrons trapped by both the AlGaN barrier trap and the surface state under stress lead to this phenomenon,and surface state recovery is the major reason for the recovery of device parameters.