Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V_ds of 5.0 V is suppressed, whereas the drain leakage current at V_ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.     

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress (NBS) is observed for amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs), which can recover in a short time. After comparing with the degradation phenomena under negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias illumination stress (PBIS), degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies ($V_{\mathrm{o}}^{+}$) in addition to the commonly reported doubly charged oxygen vacancies ($V_{\mathrm{o}}^{2+}$). Furthermore, the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of $V_{\mathrm{o}}^{+}$ under positive gate bias. The proposed degradation mechanisms are verified by TCAD simulation.     

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

超薄栅下LDD nMOSFET器件GIDL应力下退化特性

对1.4nm超薄栅LDD nMOSFET器件栅致漏极泄漏GIDL(gate-induced drain leakage)应力下的阈值电压退化进行了研究.GIDL应力中热空穴注进LDD区界面处并产生界面态，这导致器件的阈值电压变大.相同栅漏电压V_DG下的不同GIDL应力后阈值电压退化量的对数与应力V_D/V_DG的比值成正比.漏偏压V_D不变的不同GIDL应力后阈值电压退化随着应力中栅电压的增大而增大，相同栅偏压V_G下的不同GIDL应力后阈值电压退化也随着应力中漏电压的增大而增大，这两种应力情形下退化量在半对数坐标下与应力中变化的电压的倒数成线性关系，它们退化斜率的绝对值分别为0.76和13.5.实验发现器件退化随着应力过程中的漏电压变化远大于随着应力过程中栅电压的变化. 关键词： 栅致漏极泄漏 CMOS 阈值电压 栅漏电压     

超短沟道绝缘层上硅平面场效应晶体管中热载流子注入应力导致的退化对沟道长度的依赖性

随着场效应晶体管(MOSFET)器件尺寸的进一步缩小和器件新结构的引入, 学术界和工业界对器件中热载流子注入(hot carrier injections, HCI)所引起的可靠性问题日益关注. 本文研究了超短沟道长度(L=30–150 nm)绝缘层上硅(silicon on insulator, SOI)场效应晶体管在HCI应力下的电学性能退化机理. 研究结果表明, 在超短沟道情况下, HCI 应力导致的退化随着沟道长度变小而减轻. 通过研究不同栅长器件的恢复特性可以看出, 该现象是由于随着沟道长度的减小, HCI应力下偏压温度不稳定性效应所占比例变大而导致的. 此外, 本文关于SOI器件中HCI应力导致的退化和器件栅长关系的结果与最近报道的鳍式场效晶体管(FinFET)中的结果相反. 因此, 在超短沟道情况下, SOI平面MOSFET器件有可能具有比FinFET器件更好的HCI可靠性.     

Degradation characteristics and mechanism of PMOSFETs under NBT--PBT--NBT stress

Degradation characteristics of PMOSFETs under negative bias temperature--positive bias temperature--negative bias temperature (NBT--PBT--NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.     

Low power fluorine plasma effects on electrical reliability of AlGaN/GaN high electron mobility transistor

The new electrical degradation phenomenon of the AlGaN/GaN high electron mobility transistor(HEMT) treated by low power fluorine plasma is discovered. The saturated current, on-resistance, threshold voltage, gate leakage and breakdown voltage show that each experiences a significant change in a short time stress, and then keeps unchangeable. The migration phenomenon of fluorine ions is further validated by the electron redistribution and breakdown voltage enhancement after off-state stress. These results suggest that the low power fluorine implant ion stays in an unstable state. It causes the electrical properties of AlGaN/GaN HEMT to present early degradation. A new migration and degradation mechanism of the low power fluorine implant ion under the off-stress electrical stress is proposed. The low power fluorine ions would drift at the beginning of the off-state stress, and then accumulate between gate and drain nearby the gate side. Due to the strong electronegativity of fluorine, the accumulation of the front fluorine ions would prevent the subsequent fluorine ions from drifting, thereby alleviating further the degradation of AlGaN/GaN HEMT electrical properties.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

超深亚微米PMOS器件的NBTI退化机理

对超深亚微米PMOS器件的负栅压温度不稳定性(NBTI)退化机理进行了研究.主要集中在对器件施加NBT和随后的PBT应力后器件阈值电压的漂移上.实验证明反型沟道中空穴在栅氧中的俘获以及氢分子在栅氧中的扩散是引起NBTI退化的主要原因.当应力条件变为PBT时，陷落的空穴可以快速退陷，但只有部分氢分子可以扩散回栅氧与衬底界面钝化硅悬挂键，这就导致了PBT条件下阈值电压只能部分恢复. 关键词： 超深亚微米PMOS器件 负偏压温度不稳定性 界面陷阱 氢气     

双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

场板结构AlGaN/GaN HEMT的电流崩塌机理

在不同的漏偏压下,研究了钝化和不同场板尺寸AlGaN/GaN HEMT对电流崩塌的抑制能力.实验结果表明,钝化器件对电流崩塌的抑制能力随着漏偏压的升高而显著下降;在高漏偏压下,场板的尺寸对器件抑制崩塌的能力有较大影响,而合适尺寸的场板结构在各个漏偏压下都能够很好的抑制电流崩塌.深入分析发现,场板结构不仅能够抑制虚栅的充电过程,而且提供了放电途径,有利于虚栅的放电,从而抑制电流崩塌.在此基础上,通过建立场板介质对虚栅放电的模型,解释了高漏偏压下场板的尺寸对器件抑制崩塌的能力有较大影响的原因. 关键词： AlGaN/GaN HEMT 场板 电流崩塌     

场板结构AlGaN/GaN HEMT的电流崩塌机理

在不同的漏偏压下，研究了钝化和不同场板尺寸AlGaN/GaN HEMT对电流崩塌的抑制能力.实验结果表明，钝化器件对电流崩塌的抑制能力随着漏偏压的升高而显著下降；在高漏偏压下，场板的尺寸对器件抑制崩塌的能力有较大影响，而合适尺寸的场板结构在各个漏偏压下都能够很好的抑制电流崩塌.深入分析发现，场板结构不仅能够抑制虚栅的充电过程，而且提供了放电途径，有利于虚栅的放电，从而抑制电流崩塌.在此基础上，通过建立场板介质对虚栅放电的模型，解释了高漏偏压下场板的尺寸对器件抑制崩塌的能力有较大影响的原因.     

Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal--oxide--semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electron--hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.     

The role of metal contacts in the stability of n-type organic field effect transistors

We are presenting a long-time bias stress stability of C₆₀-based n-type organic field effect transistors (OFETs), in bottom gate, top contacts configuration, with aluminium (Al), silver (Ag) and gold (Au) source–drain contacts. The results clearly shows that the bias stress effects in C₆₀-based n-type OFETs is similar to p-type OFETs and it can be reduced by using an appropriate metal for the source–drain contacts. During the bias stress time, the threshold voltage shift and an increase in the contacts resistance have also been measured. On the basis of the stability of the device parameters, it is proposed that the Al source–drain contact-based devices gives better stability as compared to the devices with Ag and Au source–drain contacts. Our results show that the bias stress-induced threshold voltage shift is due to the trapping of charges in the channel region and in the vicinity of the source–drain contacts.     

The effect of barrier strain on the reliability of Inx Al1–xN/AlN/GaN heterostructure field‐effect transistors

We report on the reliability of In_x Al_1–xN/AlN/GaN‐based heterostructure field‐effect transistors (HFETs) fabricated on five different wafers with varying indium compositions (0.12 ≤ x ≤ 0.20) encompassing the tensile/compressive strain fields. All of the tested devices underwent high field on‐state stress at 20 V DC drain bias and zero gate bias for five hours. We monitored the drain current and low‐frequency noise (LFN) a priori and a posteriori the stress treatment to quantify device degradation. HFETs suffering tensile strain showed remarkably large degradation which manifested itself with up to 25 dB increase in noise power and up to 72% loss of drain current after stress. On the other hand, devices fabricated on compressively strained structures remained intact after stress, but they had about 30 dB higher pre‐stress noise‐power levels and about 50% lower drain‐current densities to begin with. The results show that the nearly lattice‐matched In_0.17Al_0.83N barrier exhibited very low degradation along with current density remaining high compared with the devices having barriers with lower or higher indium content. Our results suggest that the nearly‐lattice‐matched InAlN can be a good candidate for devices due to its relatively better reliability while maintaining a high current density. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Actions of negative bias temperature instability (NBTI) and hot carriers in ultra-deep submicron p-channel metal——oxide——semiconductor field-effect transistors (PMOSFETs)

Hot carrier injection (HCI) at high temperatures and different values of gate bias V_g has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at V_g=V_d, where V_d is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal--oxide--semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.     

高场应力及栅应力下AlGaN/GaN HEMT器件退化研究

采用不同的高场应力和栅应力对AlGaN/GaN HEMT器件进行直流应力测试,实验发现：应力后器件主要参数如饱和漏电流,跨导峰值和阈值电压等均发生了明显退化,而且这些退化还是可以完全恢复的;高场应力下,器件特性的退化随高场应力偏置电压的增加和应力时间的累积而增大;对于不同的栅应力,相对来说,脉冲栅应力和开态栅应力下器件特性的退化比关态栅应力下的退化大.对不同应力前后器件饱和漏电流,跨导峰值和阈值电压的分析表明,AlGaN势垒层陷阱俘获沟道热电子以及栅极电子在栅漏间电场的作用下填充虚栅中的表面态是这些不同应 关键词： AlGaN/GaN HEMT器件 表面态(虚栅) 势垒层陷阱 应力     

新型槽栅PMOSFET热载流子退化机理与抗热载流子效应研究

分析了槽栅器件中的热载流子形成机理,发现在三个应力区中,中栅压附近热载流子产生概率达到最大.利用先进的半导体器件二维器件仿真器研究了槽栅和平面PMOSFET的热载流子特 性,结果表明槽栅器件中热载流子的产生远少于平面器件,且对于栅长在深亚微米和超深亚 微米情况下尤为突出.为进一步探讨热载流子加固后对器件特性的其他影响,分别对不同种 类和浓度的界面态引起的器件栅极和漏极特性的漂移进行了研究,结果表明同样种类和密度 的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件.为开展深亚微米和亚0.1微米 新型槽栅 关键词： 槽栅PMOSFET 热载流子退化机理 热载流子效应