High-field-induced electron detrapping in An AlGaN/GaN high electron mobility transistor

A step stress test is carried out to study the reliability characteristics of an AlGaN/GaN high electron mobility transistor(HEMT).An anomalous critical drain-to-gate voltage with a negative temperature coefficient is observed in the stress sequence,beyond which the HEMT device starts to recover from degradation induced by early lower voltage stress.While the performance degradation featuring the drain current slump stems from electron trapping in the surface or bulk states during low-to-medium bias stress,the recovery is attributed to high field induced electron detrapping.The carrier detrapping mechanism could be helpful for lessening the trapping-related performance degradation of a GaN-based HEMT.     

Degradation characteristics and mechanism of PMOSFETs under NBT--PBT--NBT stress

Degradation characteristics of PMOSFETs under negative bias temperature--positive bias temperature--negative bias temperature (NBT--PBT--NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.     

Study on the negative bias temperature instability effect under dynamic stress

This paper studies negative bias temperature instability (NBTI) under alternant and alternating current (AC) stress.Under alternant stress,the degradation smaller than that of single negative stress is obtained.The smaller degradation is resulted from the recovery of positive stress.There are two reasons for the recovery.One is the passivation of H dangling bonds,and another is the detrapping of charges trapped in the oxide.Under different frequencies of AC stress,the parameters all show regular degradation,and also smaller than that of the direct current stress.The higher the frequency is,the smaller the degradation becomes.As the negative stress time is too small under higher frequency,the deeper defects are hard to be filled in.Therefore,the detrapping of oxide charges is easy to occur under positive bias and the degradation is smaller with higher frequency.     

New aspects of HCI test for ultra-short channel n-MOSFET devices

Hot carriers injection (HCI) tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices (75--90\,nm), which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage ($V_{\rm d}$) stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different $V_{\rm d}$ stresses in order to understand the relations between peak of substrate current ($I_{\rm sub}$) and channel length/stress voltage.     

Negative bias-induced threshold voltage instability and zener/interface trapping mechanism in GaN-based MIS-HEMTs

We investigate the instability of threshold voltage in D-mode MIS-HEMT with in-situ SiN as gate dielectric under different negative gate stresses.The complex non-monotonic evolution of threshold voltage under the negative stress and during the recovery process is induced by the combination effect of two mechanisms.The effect of trapping behavior of interface state at SiN/AlGaN interface and the effect of zener traps in AlGaN barrier layer on the threshold voltage instability are opposite to each other.The threshold voltage shifts negatively under the negative stress due to the detrapping of the electrons at SiN/AlGaN interface,and shifts positively due to zener trapping in AlGaN barrier layer.As the stress is removed,the threshold voltage shifts positively for the retrapping of interface states and negatively for the thermal detrapping in AlGaN.However,it is the trapping behavior in the AlGaN rather than the interface state that results in the change of transconductance in the D-mode MIS-HEMT.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Time-dependent degradation of threshold voltage in AlGaN/GaN high electron mobility transistors

This paper gives a detailed analysis of the time-dependent degradation of the threshold voltage in AlGaN/GaN high electron mobility transistors(HEMTs) submitted to off-state stress. The threshold voltage shows a positive shift in the early stress, then turns to a negative shift. The negative shift of the threshold voltage seems to have a long recovery time. A model related with the balance of electron trapping and detrapping induced by shallow donors and deep acceptors is proposed to explain this degradation mode.     

Study on the recovery of NBTI of ultra-deep sub-micro MOSFETs

Taking the actual operating condition of complementary metal oxide semiconductor (CMOS) circuit into account, conventional direct current (DC) stress study on negative bias temperature instability (NBTI) neglects the detrapping of oxide positive charges and the recovery of interface states under the `low' state of p-channel metal oxide semiconductor field effect transistors (MOSFETs) inverter operation. In this paper we have studied the degradation and recovery of NBTI under alternating stress, and presented a possible recovery mechanism. The three stages of recovery mechanism under positive bias are fast recovery, slow recovery and recovery saturation.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Fluorine-plasma treated AlGaN/GaN high electronic mobility transistors under off-state overdrive stress

Influences of off-state overdrive stress on the fluorine-plasma treated AlGaN/GaN high-electronic mobility transistors (HEMTs) are experimentally investigated. It is observed that the reverse leakage current between the gate and source decreases after the off-state stress, whereas the current between the gate and drain increases. By analyzing those changes of the reverse currents based on the Frenkel-Poole model, we realize that the ionization of fluorine ions occurs during the off-state stress. Furthermore, threshold voltage degradation is also observed after the off-state stress, but the degradations of AlGaN/GaN HEMTs treated with different F-plasma RF powers are different. By comparing the differences between those devices, we find that the F-ions incorporated in the GaN buffer layer play an important role in averting degradation. Lastly, suggestions to obtain a more stable fluorine-plasma treated AlGaN/GaN HEMT are put forwarded.     

Electrical bistable devices using composites of zinc sulfide nanoparticles and poly-(N-vinylcarbazole)

N-dodecanethiol capped zinc sulfide(Zn S) nanocrystals were synthesized by the one-pot approach and blended with poly(N-vinylcarbazole)(PVK) to fabricate electrical bistable devices. The corresponding devices did exhibit electrical bistability and negative differential resistance(NDR) effects. A large ON/OFF current ratio of 104 at negative voltages was obtained by applying different amplitudes of sweeping voltage. The observed conductance switching and the negative differential resistance are attributed to the electric-field-induced charge transfer between the nanocrystals and the polymer,and the charge trapping/detrapping in the nanocrystals.     

电离辐射环境下的部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管可靠性研究

随着半导体技术的进步, 集成小尺寸绝缘体上硅器件的芯片开始应用到航空航天领域, 使得器件在使用中面临了深空辐射环境与自身常规可靠性的双重挑战. 进行小尺寸器件电离辐射环境下的可靠性试验有助于对器件综合可靠性进行评估. 参照国标GB2689.1-81恒定应力寿命试验与加速寿命试验方法总则进行电应力选取, 对部分耗尽绝缘体上硅n型金属氧化物半导体场效应晶体管进行了电离辐射环境下的常规可靠性研究. 通过试验对比, 定性地分析了氧化物陷阱电荷和界面态对器件敏感参数的影响, 得出了氧化物陷阱电荷和界面态随着时间参数的变化, 在不同阶段对器件参数的影响. 结果表明, 总剂量效应与电应力的共同作用将加剧器件敏感参数的退化, 二者的共同作用远大于单一影响因子.     

Comparison of hot-hole injections in ultrashort channel LDD nMOSFETs with ultrathin oxide under an alternating stress

The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain (LDD) nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection (LGVHHI), gate-induced drain leakage induced hot-hole injection (GIDLIHHI) and substrate hot-hole injection (SHHI), have different influences on the devices damaged already by the previous hot electron injection (HEI) because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device's performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.     

Evaluation of negative bias temperature instability in ultra-thin gate oxide pMOSFETs using a new on-line PDO method

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by I_D-V_D characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction--diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90\du\ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction--diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction--diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.     

Degradation and its fast recovery in a-IGZO thin-film transistors under negative gate bias stress

A new type of degradation phenomena featured with increased subthreshold swing and threshold voltage after negative gate bias stress (NBS) is observed for amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs), which can recover in a short time. After comparing with the degradation phenomena under negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias illumination stress (PBIS), degradation mechanisms under NBS is proposed to be the generation of singly charged oxygen vacancies ($V_{\mathrm{o}}^{+}$) in addition to the commonly reported doubly charged oxygen vacancies ($V_{\mathrm{o}}^{2+}$). Furthermore, the NBS degradation phenomena can only be observed when the transfer curves after NBS are measured from the negative gate bias to the positive gate bias direction due to the fast recovery of $V_{\mathrm{o}}^{+}$ under positive gate bias. The proposed degradation mechanisms are verified by TCAD simulation.     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

Kink effect in current–voltage characteristics of a GaN-based high electron mobility transistor with an AlGaN back barrier

The kink effect in current–voltage(IV)characteristic s seriously deteriorates the performance of a GaN-based HEMT.Based on a series of direct current(DC)IV measurements in a GaN-based HEMT with an AlGaN back barrier,a possible mechanism with electron-trapping and detrapping processes is proposed.Kink-related deep levels are activated by a high drain source voltage(Vds)and located in a GaN channel layer.Both electron trapping and detrapping processes are accomplished with the help of hot electrons from the channel by impact ionization.Moreover,the mechanism is verified by two other DC IV measurements and a model with an expression of the kink current.     

Subthreshold regime in rubrene single-crystal organic transistors

Organic field-effect transistors were fabricated with vapor-grown rubrene single crystals in a staggered top-contact configuration. The devices were electrically characterized by measuring the transfer curves at low drain voltage. In parallel to these measurements, a model is developed to account for the subthreshold regime of the transistors. The model is based on the multiple trapping and thermal release concept, which assumes that charge transport is limited by a single level of shallow traps located close to the transport band edge. It is shown that the threshold voltage no longer establishes at the transition between the depletion and accumulation regimes. Instead, the threshold corresponds to the point at which traps are filled. This results in a subthreshold current that varies linearly with gate voltage. Moreover, the subthreshold current at low drain voltages increases with drain voltage. These finding are in good agreement with the experimental data.     

Long-term stability of InP MIS devices

Room-temperature bias stress measurements were performed on n-type InP MIS capacitors. A wide range of interface passivation processes and gate dielectrics was investigated. A generally observed behaviour under positive bias stress is a slow trapping - fast detrapping consistent with a trap distribution in the interfacial layer above the conduction band edge of InP. Large variations both in the magnitude and in the time dependence of the flat-band voltage shift ΔV_FB are observed. We discuss these drift behaviours in terms of interface traps - rather than bulk dielectric traps - in relation with the physico-chemical properties of the interface. It is shown that devices based on InP treated by annealing under arsenic pressure and controlled oxidation exhibit a very good stability. For any passivation procedure, the drift is strongly diminished if the device is stressed with AC voltage compared to DC voltage.     

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal--Oxide--Semiconductor Field Effect Transistor

A novel fully depleted air A1N silicon-on-insulator （SOD metai-oxide-semiconductor field effect transistor （MOS- FET） is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75K higher than the atmosphere temperature, while the lattice temperature is just 4 K higher than the atmosphere temperature resulting in less severe self-heating effect in air A1N SOI MOSFETs and A1N SOI MOSFETs. The on-state current of air A1N SOI MOSFETs is similar to the A1N SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of A1N SOI is 6. 7 times of normal SOI MOSFETs, while the counterpart of air A1N SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air A1N SOl MOSFETs with different drain voltage is much less than that of A1N SOI devices, when the drain voltage is Mased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured.