A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p$+$ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p$+$ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance ($R_{\rm on,sp}$). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage ($V_{\rm BR}$) and $R_{\rm on,sp}$ ($V_{\rm BR}^{2}R_{\rm on,sp}$) of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.     

Improvement of reverse blocking performance in vertical power MOSFETs with Schottky–drain-connected semisuperjunctions

To enhance the reverse blocking capability with low specific on-resistance,a novel vertical metal-oxidesemiconductor field-effect transistor(MOSFET) with a Schottky-drian(SD) and SD-connected semisuperjunctions(SDD-semi-SJ),named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional(2D) numerical simulations.The SD contacted with the n-pillar exhibits the Schottky-contact property,and that with the p-pillar the Ohmic-contact property.Based on these features,the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions(SJ) or semisuperjunctions(semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage(BV) and the specific on-resistance(R_(on)A).For a given pillar width and n-drift thickness,there exists a proper range of n-drift concentration(N),in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of R_(on)A-BV compared to the predication of SJ MOSFET in the forward applications.And what is much valuable,in this proper range of N,the desired BV and good trade-off could be achieved only by determining the pillar thickness,with the top assist layer thickness unchanged.Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of R_(on)A-BV improvement in SD-D-semi-SJ MOSFET.These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications.     

Superjunction nanoscale partially narrow mesa IGBT towards superior performance

We present a detailed study of a superjunction(SJ) nanoscale partially narrow mesa(PNM) insulated gate bipolar transistor(IGBT) structure. This structure is created by combining the nanoscale PNM structure and the SJ structure together. It demonstrates an ultra-low saturation voltage(V_(ce(sat))) and low turn-off loss(E_(off)) while maintaining other device parameters. Compared with the conventional 1.2 k V trench IGBT, our simulation result shows that the V_(ce(sat))of this structure decreases to 0.94 V, which is close to the theoretical limit of 1.2 k V IGBT. Meanwhile, the fall time decreases from109.7 ns to 12 ns and the E off is down to only 37% of that of the conventional structure. The superior tradeoff characteristic between V_(ce(sat))and E_(off) is presented owing to the nanometer level mesa width and SJ structure. Moreover, the short circuit degeneration phenomenon in the very narrow mesa structure due to the collector-induced barriers lowering(CIBL) effect is not observed in this structure. Thus, enough short circuit ability can be achieved by using wide, floating P-well technique.Based on these structure advantages, the SJ-PNM-IGBT with nanoscale mesa width indicates a potentially superior overall performance towards the IGBT parameter limit.     

An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction (SJ) MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.     

具有部分超结的新型SiC SBD特性分析

提出了一种具有部分超结（super junction, SJ）结构的新型SiC肖特基二极管,命名为SiC Semi-SJ-SBD结构,通过将常规SBD耐压区分为常规耐压区和超结耐压区来减小导通电阻,改善正向特性.利用二维器件模拟软件MEDICI仿真分析,研究了不同超结深度和厚度时击穿电压(V_B)和比导通电阻(R_on-sp),与常规结构的SBD比较得出,半超结结构可以明显改善SiC肖特基二极管特性,并得到优化的设计方案,选择超结宽度2< 关键词： SiC肖特基二极管 super junction 导通电阻 击穿电压     

Comprehensive study of a 4H–SiC MES–MOSFET

In this paper, we studied the enhancement of the breakdown voltage in the 4H–SiC MESFET–MOSFET (MES–MOSFET) structure which we have proposed in our previous work. We compared this structure with Conventional Bulk-MOSFET (CB-MOSFET) and Field plated Conventional Bulk-MOSFET (FCB-MOSFET) structures. The 4H–SiC MES–MOSFET structure consists of two additional schottky buried gates which behave like a Metal on Semiconductor (MES) at the interface of the active region and substrate. The motivation for this structure was to enhance the breakdown voltage by introducing a new technique of utilizing the reduced surface field (RESURF) concept. In our comparison and investigation we used a two-dimensional device simulator. Our simulation results show that the breakdown voltage of the proposed structure is 3.7 and 2.9 times larger than CB-MOSFET and FCB-MOSFET structures, respectively. We also showed that the threshold voltage and the slope of drain current (I_D) as a function of drain–source voltage (V_DS) for all the structures is the same.     

SiC1-xGex/SiC 异质结光电二极管特性的研究

使用二维器件模拟软件Medici, 对SiC_1-xGe_x/SiC异质结的光电特性进行了模拟.设计了N型重掺杂SiC层的厚度为1 μm, P型轻掺杂SiC_1-xGe_x层厚为0.4 μm, 二者之间形成突变异质结.在反向偏压3 V、光强度为 0.23 W/cm²的条件下, p-n+ SiC_0.8Ge_0.2/SiC和p-n+ SiC_0.7Ge_0.3/SiC敏感波长λ分别可以达到0.64 μm和0.7 μm, 光电流分别为7.765×10^－7 A/μm和7.438×10^－7 A/μm; 为了进一步提高SiC_1-xGe_x/SiC 异质结的光电流, 我们把p-n+两层结构改进为p-i-n三层结构.在同样的偏压、光照条件下, p-i-n SiC_0.8Ge_0.2/SiC和p-i-n SiC_0.7Ge_0.3/SiC的光电流分别达到1.6734×10－6 A/μm和1.844×10－6 A/μm.     

A super junction SiGe low-loss fast switching power diode

This paper proposes a novel super junction (SJ) SiGe switching power diode which has a columnar structure of alternating p^- and n^- doped pillar substituting conventional n^- base region and has far thinner strained SiGe p⁺ layer to overcome the drawbacks of existing Si switching power diode. The SJ SiGe diode can achieve low specific on-resistance, high breakdown voltages and fast switching speed. The results indicate that the forward voltage drop of SJ SiGe diode is much lower than that of conventional Si power diode when the operating current densities do not exceed 1000 A/cm², which is very good for getting lower operating loss. The forward voltage drop of the Si diode is 0.66V whereas that of the SJ SiGe diode is only 0.52 V at operating current density of 10 A/cm². The breakdown voltages are 203 V for the former and 235 V for the latter. Compared with the conventional Si power diode, the reverse recovery time of SJ SiGe diode with 20 per cent Ge content is shortened by above a half and the peak reverse current is reduced by over 15%. The SJ SiGe diode can remarkably improve the characteristics of power diode by combining the merits of both SJ structure and SiGe material.     

Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal-oxide-semiconductor field-effect transistor(MOSFET)under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation.The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track.The time for energy deposition in SiC is on the order of picoseconds.The TCAD is used to simulate the single event burnout(SEB)sensitivity of SiC MOSFET at four representative incident positions and four incident depths.When heavy ions strike vertically from SiC MOSFET source electrode,the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer,strike from the channel,and strike from the body diode region.High current and strong electric field simultaneously appear in the local area of SiC MOSFET,resulting in excessive power dissipation,further leading to excessive high lattice temperature.The gate-source junction area and the substrate-epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature.In the SEB simulation of SiC MOSFET at different incident depths,when the incident depth does not exceed the device's epitaxial layer,the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.     

固态Marx发生器的过流保护研究

具有快速上升沿、低开关损耗的SiC MOSFET已逐渐在固态高压脉冲电源中使用。针对固态Marx发生器中的常见短路故障,分析了SiC MOSFET的过流损坏机制,提出了一种新型的带过流保护的驱动系统。该驱动系统不仅实现了宽驱动信号同步输出,同时能够在整个SiC MOSFET导通期间提供过电流钳制效果。驱动系统中的保护电路利用SiC MOSFET门极电压与漏极电流的关系,通过单个采样电阻和一对反向串联的稳压管将SiC MOSFET门极电压拉低的方式来限制过电流。实验结果表明:当开关管的导通电流较小时,虽然门极电压会有轻微下降,但是SiC MOSFET的导通阻抗仍然很低;而在过电流故障发生时,门极电压会被快速拉低,开关管的导通阻抗急剧上升,从而迅速将导通电流钳制在安全范围内。     

Improved 4H-SiC UMOSFET with super-junction shield region

This article investigates an improved 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance ($R_{\rm on,sp}$). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field ($E$-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that $R_{\rm on,sp }$ of the modified structure, and breakdown voltage ($V_{\rm BR}$) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit (${\rm FOM}=V^{2}_{\rm BR}/R_{\rm on,sp}$) is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge ($Q_{\rm gd}$) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the $V_{\rm BR}$ of the device without degradation of dynamic performance.     

A 3D SiC MOSFET with poly-silicon/SiC heterojunction diode

A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively.     

6H-SiC肖特基源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET——6H-SiC肖特基源漏MOSFET.这种器件结构制备工艺简单，避 免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高、晶格损伤大，注入激活 率低等问题.分析了该器件的电流输运机理，并通过MEDICI模拟，给出了SiC肖特基源漏MOSF ET伏安特性以及其和金属功函数、栅氧化层厚度和栅长关系. 关键词： 碳化硅 肖特基接触 MOSFET 势垒高度     

n,p柱宽度对超结SiGe功率二极管电学特性的影响

结合SiGe材料的优异性能与超结结构在功率器件方面的优势,提出了一种超结SiGe功率二极管.该器件有两个重要特点:一是由轻掺杂的p型柱和n型柱相互交替形成超结结构,取代传统功率二极管的n^-基区;二是阳极p⁺区采用很薄的应变SiGe材料.该二极管可以克服常规Si p⁺n^-n⁺功率二极管存在的一些缺陷,如阻断电压增大的同时,正向导通压降随之增大,反向恢复时间也变长.利用二维器件模拟软件MEDICI仿真 关键词： 超结 锗硅二极管 n p柱宽度 电学特性     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

Porous AlN films grown on C-face SiC by hydride vapor phase epitaxy

We report the growth of porous AlN films on C-face SiC substrates by hydride vapor phase epitaxy (HVPE). The influences of growth condition on surface morphology, residual strain and crystalline quality of AlN films have been investigated. With the increase of the V/III ratio, the growth mode of AlN grown on C-face 6H-SiC substrates changes from step-flow to pit-hole morphology. Atomic force microscopy (AFM), scanning electron microscopy (SEM) and Raman analysis show that cracks appear due to tensile stress in the films with the lowest V/III ratio and the highest V/III ratio with a thickness of about 3 μm. In contrast, under the medium V/III ratio growth condition, the porous film can be obtained. Even when the thickness of the porous AlN film is further increased to 8 μm, the film remains porous and crack-free, and the crystal quality is improved.     

MOSFET调制器的实验研究

 介绍了MOSFET调制器的基本原理，并对其并联分流和感应叠加两种开关结构进行了实验研究。基于可编辑逻辑器件设计了其触发电路，驱动电路采用高速MOSFET对管组成的推挽输出形式，加快了MOSFET的开关速度。利用Pspice软件对开关上有无剩余电流电路(RCD)两种情况进行仿真，结果表明，加装RCD电路可以有效吸收MOSFET在关断瞬间产生的反峰电压。实验中，电流波形用Pearson线圈测量，用3个MOSFET并联作开关，当电容充电电压为450 V，负载为30 Ω时，脉冲电流13 A，前沿20 ns，平顶约80 ns；用3个单元调制器感应叠加，当电容充电电压为450 A，负载为30 Ω时，脉冲电流强度为40 A，前沿25 ns，平顶约70 ns。     

Design of high-repetition frequency gating circuit for cathode of image intensifier北大核心CSCD

According to the requirements of high repetition frequency, fast edge speed and small pulse width for cathode gating signal by range-gated technology, a cathode high repetition frequency gating circuit using period and multi-stage acceleration was proposed. By combining the RC circuit and the high-speed gate circuit, the time bias circuit unit was cascaded to generate logic pulses with different time sequences, which could respectively control the intermediate stage drive MOSFET to generate three phased drive signals, and the output of the intermediate stage drive was used as input of the output-stage MOSFET to control the acceleration and retention of its on-off process. It was verified by software simulation and board-level test. The test results show that the proposed gating circuit can increase the edge time of output pulse from μs level to 2 ns, and can provide +50 V/−200 V cathode off/on voltage, so as to achieve a repetition frequency ranging from 0~350 kHZ, a duty ratio of 0~100%, a minimum pulse width of 3.7 ns, and a pulse output delay time jitter of about 0.1 ns. It has important guiding significance for improving the minimum pulse width performance of high-speed and high-voltage gating power, the highest working repetition frequency and reducing the power loss of the device. © 2022 Editorial office of Journal of Applied Optics. All rights reserved.     

基于位相分布限制衍射光学元件的散斑抑制方法

根据散斑产生的机理,利用像素点之间干涉的概念,提出了通过限制光场的位相分布范围来抑制投影图像中散斑对比度的方法.在部分发展散斑的条件下,推导了位相均匀分布情况下的散斑对比度公式,揭示了当相位分布范围在0.6π~2π之间时,散斑对比度随相位分布范围的变化而震荡变化,当把相位分布范围限制在0.6π以下时,散斑对比度会随相位分布范围的减小而迅速下降.建立了理想仿真模型和实际仿真模型来验证该方法的正确性和可行性.在理想仿真模型中,当位相分布范围从2π变到0,所得散斑图样对比度从66.44%降到0;在实际仿真模型中,模拟了实际激光投影系统的光路结构,并运用了两片衍射光学元件,一片用于激光整形匀化,一片用于光场的位相分布范围限制,散斑图样对比度从92.78%降低到2.09%.该方法稳定性高、耗能低、使用元件尺寸小,为全息投影显示的散斑抑制提供了参考.     

600 A重复频率脉冲恒流源研制北大核心CSCD

针对国内脉冲恒流源幅值较小、重复频率较低等问题,设计了基于电流闭环反馈控制的恒流电路,建立了相应的数学模型,并采用Pspice仿真验证了电路的功能,最终研制了1台600 A重复频率工作的脉冲恒流电源。电源采取储能放电配合高速开关的工作模式,使用功率场效应三极管作为线性调整开关,可大范围自动恒流,适用于激光二极管负载。输出的脉冲电流幅值最高600 A,上升时间小于40μs,电压幅值最高320 V,脉宽100~600μs可调,工作重复频率最高200 Hz。电源体积较小,结构紧凑,效率可达90%以上。