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Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n~+-layer 下载免费PDF全文
A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n +-layer silicon-on-insulator (PBN SOI) is proposed in this paper.Based on the proposed expressions of the vertical interface electric field,the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I),resulting in a high breakdown voltage (BV) for the device.For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 μm),the E I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI,respectively. 相似文献
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A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively. 相似文献
3.
A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (EI) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of EI and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance. 相似文献
4.
Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer 下载免费PDF全文
A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n+-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (EI), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the EI and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively. 相似文献
5.
This paper presents a novel high-voltage lateral double diffused metal--oxide semiconductor (LDMOS) with self-adaptive interface charge (SAC) layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer (EI) and increase breakdown voltage (BV). The BV and EI of SAC LDMOS increase to 612 V and 600 V/μm from 204 V and 90.7 V/μm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of η which present the enhanced ability of interface charge on EI are defined and analysed. 相似文献
6.
This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance. 相似文献
7.
A new analytical model of high voltage silicon on insulator (SOI) thin film devices 总被引:2,自引:0,他引:2 下载免费PDF全文
A new analytical model of high voltage silicon on insulator (SOI)
thin film devices is proposed, and a formula of silicon critical
electric field is derived as a function of silicon film thickness by
solving a 2D Poisson equation from an effective ionization rate,
with a threshold energy taken into account for electron multiplying.
Unlike a conventional silicon critical electric field that is
constant and independent of silicon film thickness, the proposed
silicon critical electric field increases sharply with silicon film
thickness decreasing especially in the case of thin films, and can
come to 141V/μm at a film thickness of 0.1μm which is
much larger than the normal value of about 30V/μm. From the
proposed formula of silicon critical electric field, the expressions
of dielectric layer electric field and vertical breakdown voltage
(VB,V) are obtained. Based on the model, an ultra thin film
can be used to enhance dielectric layer electric field and so
increase vertical breakdown voltage for SOI devices because of its
high silicon critical electric field, and with a dielectric layer
thickness of 2μm the vertical breakdown voltages reach 852
and 300V for the silicon film thicknesses of 0.1 and 5μm,
respectively. In addition, a relation between dielectric layer
thickness and silicon film thickness is obtained, indicating a
minimum vertical breakdown voltage that should be avoided when an
SOI device is designed. 2D simulated results and some experimental
results are in good agreement with analytical results. 相似文献
8.
A novel partial silicon-on-insulator laterally double-diffused metal-oxide-semiconductor transistor (PSOI LDMOS) with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n+-layer, which is partially buried on the bottom interface of the top silicon layer (PBNL PSOI LDMOS). The undepleted interface n+-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage (BV). With the same thickness values of the top silicon layer (10 p.m) and buried oxide layer (0.375 μm), the BV of the PBNL PSOI LDMOS increases to 432 V from 285 V of the conventional PSOI LDMOS, which is improved by 51.6%. 相似文献
9.
A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device 总被引:1,自引:0,他引:1 下载免费PDF全文
A new partial-SOI (PSOI) high voltage device structure
called a CI PSOI (charge island PSOI) is proposed for the first time
in this paper. The device is characterized by a charge island layer
on the interface of the top silicon layer and the dielectric buried layer in
which a series of equidistant high concentration n+-regions
is inserted. Inversion holes resulting from the vertical electric field
are located in the spacing between two neighbouring n+-regions
on the interface by the force with ionized donors in the
undepleted n+-regions, and therefore effectively enhance the
electric field of the dielectric buried layer (EI) and increase
the breakdown voltage (BV), thereby alleviating the self-heating effect
(SHE) by the silicon window under the source. An analytical model of
the vertical interface electric field for the CI PSOI is presented
and the analytical results are in good agreement with the 2D
simulation results. The BV and EI of the CI PSOI LDMOS increase to
631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the
conventional PSOI with a lower SHE, respectively. The effects of the
structure parameters on the device characteristics are analysed for the
proposed device in detail. 相似文献
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