Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal-oxide-semiconductor field-effect transistor(MOSFET)under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation.The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track.The time for energy deposition in SiC is on the order of picoseconds.The TCAD is used to simulate the single event burnout(SEB)sensitivity of SiC MOSFET at four representative incident positions and four incident depths.When heavy ions strike vertically from SiC MOSFET source electrode,the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer,strike from the channel,and strike from the body diode region.High current and strong electric field simultaneously appear in the local area of SiC MOSFET,resulting in excessive power dissipation,further leading to excessive high lattice temperature.The gate-source junction area and the substrate-epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature.In the SEB simulation of SiC MOSFET at different incident depths,when the incident depth does not exceed the device's epitaxial layer,the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.     

SiC肖特基源漏MOSFET的阈值电压

SiC肖特基源漏MOSFET的阈值电压不同于传统的MOSFET的阈值电压.在深入分析工作机理的基础上,利用二维模拟软件ISE提取并分析了器件的阈值电压.对SiC肖特基源漏MOSFET的阈值电压给出物理描述,得出当源极载流子主要以场发射方式进入沟道,同时沟道进入强反型状态,此时的栅电压是该器件的阈值电压. 关键词： 碳化硅 肖特基接触 阈值电压     

6H-SiC肖特基源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET——6H-SiC肖特基源漏MOSFET.这种器件结构制备工艺简单，避 免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高、晶格损伤大，注入激活 率低等问题.分析了该器件的电流输运机理，并通过MEDICI模拟，给出了SiC肖特基源漏MOSF ET伏安特性以及其和金属功函数、栅氧化层厚度和栅长关系. 关键词： 碳化硅 肖特基接触 MOSFET 势垒高度     

固态Marx发生器的过流保护研究

具有快速上升沿、低开关损耗的SiC MOSFET已逐渐在固态高压脉冲电源中使用。针对固态Marx发生器中的常见短路故障,分析了SiC MOSFET的过流损坏机制,提出了一种新型的带过流保护的驱动系统。该驱动系统不仅实现了宽驱动信号同步输出,同时能够在整个SiC MOSFET导通期间提供过电流钳制效果。驱动系统中的保护电路利用SiC MOSFET门极电压与漏极电流的关系,通过单个采样电阻和一对反向串联的稳压管将SiC MOSFET门极电压拉低的方式来限制过电流。实验结果表明:当开关管的导通电流较小时,虽然门极电压会有轻微下降,但是SiC MOSFET的导通阻抗仍然很低;而在过电流故障发生时,门极电压会被快速拉低,开关管的导通阻抗急剧上升,从而迅速将导通电流钳制在安全范围内。     

An oxide filled extended trench gate super junction MOSFET structure

This paper proposes an oxide filled extended trench gate super junction (SJ) MOSFET structure to meet the need of higher frequency power switches application. Compared with the conventional trench gate SJ MOSFET, new structure has the smaller input and output capacitances, and the remarkable improvements in the breakdown voltage, on-resistance and switching speed. Furthermore, the SJ in the new structure can be realized by the existing trench etching and shallow angle implantation, which offers more freedom to SJ MOSFET device design and fabrication.     

High-power SiC MESFET using dual p-buffer layer for S-band power amplifier

Silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is fabricated by using a standard SiC MESFET structure with the application of a dual p-buffer layer and a multi-recessed gate to the process for S-band power amplifier. The lower doped upper-buffer layer serves to maintain the channel current, while the higher doped lower-buffer layer is used to provide excellent electron confinement in the channel layer. A 20-mm gate periphery SiC MESFET biased at a drain voltage of 85 V demonstrates a pulsed wave saturated output power of 94 W, a linear gain of 11.7 dB, and a maximum power added efficiency of 24.3% at 3.4 GHz. These results are improved compared with those of the conventional single p-buffer MESFET fabricated in this work using the same process. A radio-frequency power output greater than 4.7 W/mm is achieved, showing the potential as a high-voltage operation device for high-power solid-state amplifier applications.     

Study on a novel vertical enhancement-mode Ga2O3 MOSFET with FINFET structure

A novel enhanced mode(E-mode)Ga₂O₃ metal-oxide-semiconductor field-effect transistor(MOSFET)with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated.It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics.The metal material of the gate,the oxide material,the oxide thickness,and the epitaxial layer concentration strongly affect the threshold voltage and the output currents.Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant.When the output current density of the device increases,the source concentration,the thickness of the epitaxial layer,and the total width of the device need to be expanded.The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage.It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga₂O₃ MOSFET requires the epitaxial layer concentration,the channel height of the device,the thickness of the source region,and the oxide thickness of the device should be less than 5×10¹⁶ cm^-3,less than 1.5μm,between 0.1μm-0.3μm and less than 0.08μm,respectively.     

High-power SiC MESFET using a dual p-buffer layer for an S-band power amplifier

A silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is fabricated by using a standard SiC MESFET structure with the application of a dual p-buffer layer and a multi-recessed gate to the process for an S-band power amplifier. The lower doped upper-buffer layer serves to maintain the channel current, while the higher doped lower-buffer layer is used to provide excellent electron confinement in the channel layer. A 20-mm gate periphery SiC MESFET biased at a drain voltage of 85 V demonstrates a pulsed wave saturated output power of 94 W, a linear gain of 11.7 dB, and a maximum power added efficiency of 24.3% at 3.4 GHz. These results are improved compared with those of the conventional single p-buffer MESFET fabricated in this work using the same process. A radio-frequency power output greater than 4.7 W/mm is achieved, showing the potential as a high-voltage operation device for high-power solid-state amplifier applications.     

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p$+$ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p$+$ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance ($R_{\rm on,sp}$). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage ($V_{\rm BR}$) and $R_{\rm on,sp}$ ($V_{\rm BR}^{2}R_{\rm on,sp}$) of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.     

Improved 4H-SiC UMOSFET with super-junction shield region

This article investigates an improved 4H-SiC trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) (UMOSFET) fitted with a super-junction (SJ) shielded region. The modified structure is composed of two n-type conductive pillars, three p-type conductive pillars, an oxide trench under the gate, and a light n-type current spreading layer (NCSL) under the p-body. The n-type conductive pillars and the light n-type current spreading layer provide two paths to and promote the diffusion of a transverse current in the epitaxial layer, thus improving the specific on-resistance ($R_{\rm on,sp}$). There are three p-type pillars in the modified structure, with the p-type pillars on both sides playing the same role. The p-type conductive pillars relieve the electric field ($E$-field) in the corner of the trench bottom. Two-dimensional simulation (silvaco TCAD) indicates that $R_{\rm on,sp }$ of the modified structure, and breakdown voltage ($V_{\rm BR}$) are improved by 22.2% and 21.1% respectively, while the maximum figure of merit (${\rm FOM}=V^{2}_{\rm BR}/R_{\rm on,sp}$) is improved by 79.0%. Furthermore, the improved structure achieves a light smaller low gate-to-drain charge ($Q_{\rm gd}$) and when compared with the conventional UMOSFET (conventional-UMOS), it displays great advantages for reducing the switching energy loss. These advantages are due to the fact that the p-type conductive pillars and n-type conductive pillars configured under the gate provide a substantial charge balance, which also enables the charge carriers to be extracted quickly. In the end, under the condition of the same total charge quantity, the simulation comparison of gate charge and OFF-state characteristics between Gauss-doped structure and uniform-doped structure shows that Gauss-doped structure increases the $V_{\rm BR}$ of the device without degradation of dynamic performance.     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

Study of a double epi-layers SiC junction barrier Schottky rectifiers embedded P layer in the drift region

<正>This paper proposes a double epi-layers 4H—SiC junction barrier Schottky rectifier(JBSR) with embedded P layer (EPL) in the drift region.The structure is characterized by the P-type layer formed in the n-type drift layer by epitaxial overgrowth process.The electric field and potential distribution are changed due to the buried P-layer,resulting in a high breakdown voltage(BV) and low specific on-resistance(R_(on,sp)).The influences of device parameters,such as the depth of the embedded P+ regions,the space between them and the doping concentration of the drift region,etc.,on BV and R_(on,sp) are investigated by simulations,which provides a particularly useful guideline for the optimal design of the device.The results indicate that BV is increased by 48.5%and Baliga's figure of merit(BFOM) is increased by 67.9%compared to a conventional 4H-SiC JBSR.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-κ gate dielectric

By solving Poisson’s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal–oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

Analysis of the effect of sidewall on the performance of 6H-SiC Schottky barrier source/drain NMOSFETs

Between source/drain and gate of SiC Schottky barrier source/drain MOSFET (SiC SBSD-MOSFET), there must be a sidewall as isolation. The width of sidewall strongly affects on the device performance. In this paper the effect of sidewall on the performance of 6H-SiC SBSD-NMOSFET is simulated with the 2D simulator MEDICI. The simulated results show that a sidewall with width less than 0.1μm slightly affects the device performance. However, when the width of sidewall exceeds 0.1μm, the conduction does not occur until the drain voltage is high enough and saturation current sharply decreases. The effect of the sidewall on device performance can be reduced by decreasing the doping concentration in the epitaxial layer.     

1200 V碳化硅功率MOSFET低温特性的实验表征及分析

碳化硅功率MOSFET是宽禁带功率半导体器件的典型代表,具有优异的电气性能。基于低温环境下的应用需求,研究了1200 V碳化硅功率MOSFET在77.7 K至300 K温区的静/动态特性,定性分析了温度对碳化硅功率MOSFET性能的影响。实验结果显示,温度从300 K降低至77.7 K时,阈值电压上升177.24%,漏-源极击穿电压降低32.99%,栅极泄漏电流降低82.51%,导通电阻升高1142.28%,零栅压漏电流降低89.84%(300 K至125 K)。双脉冲测试显示,开通时间增大8.59%,关断时间降低16.86%,开关损耗增加48%。分析发现,碳化硅功率MOSFET较高的界面态密度和较差的沟道迁移率,是导致其在低温下性能劣化的主要原因。     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.     

SiC1-xGex/SiC 异质结光电二极管特性的研究

使用二维器件模拟软件Medici, 对SiC_1-xGe_x/SiC异质结的光电特性进行了模拟.设计了N型重掺杂SiC层的厚度为1 μm, P型轻掺杂SiC_1-xGe_x层厚为0.4 μm, 二者之间形成突变异质结.在反向偏压3 V、光强度为 0.23 W/cm²的条件下, p-n+ SiC_0.8Ge_0.2/SiC和p-n+ SiC_0.7Ge_0.3/SiC敏感波长λ分别可以达到0.64 μm和0.7 μm, 光电流分别为7.765×10^－7 A/μm和7.438×10^－7 A/μm; 为了进一步提高SiC_1-xGe_x/SiC 异质结的光电流, 我们把p-n+两层结构改进为p-i-n三层结构.在同样的偏压、光照条件下, p-i-n SiC_0.8Ge_0.2/SiC和p-i-n SiC_0.7Ge_0.3/SiC的光电流分别达到1.6734×10－6 A/μm和1.844×10－6 A/μm.     

Impact of O_2 post oxidation annealing on the reliability of SiC/SiO_2 MOS capacitors

The effects of dry O_2 post oxidation annealing(POA) at different temperatures on SiC/SiO_2 stacks are comparatively studied in this paper. The results show interface trap density(Dit) of SiC/SiO_2 stacks, leakage current density(Jg), and time-dependent dielectric breakdown(TDDB) characteristics of the oxide, are affected by POA temperature and are closely correlated. Specifically, Dit, Jg, and inverse median lifetime of TDDB have the same trend against POA temperature, which is instructive for SiC/SiO_2 interface quality improvement. Moreover, area dependence of TDDB characteristics for gate oxide on SiC shows different electrode areas lead to same slope of TDDB Weibull curves.     

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-kappa gate dielectric

By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-kappa gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-kappa dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.