MOSFET调制器的实验研究

 介绍了MOSFET调制器的基本原理，并对其并联分流和感应叠加两种开关结构进行了实验研究。基于可编辑逻辑器件设计了其触发电路，驱动电路采用高速MOSFET对管组成的推挽输出形式，加快了MOSFET的开关速度。利用Pspice软件对开关上有无剩余电流电路(RCD)两种情况进行仿真，结果表明，加装RCD电路可以有效吸收MOSFET在关断瞬间产生的反峰电压。实验中，电流波形用Pearson线圈测量，用3个MOSFET并联作开关，当电容充电电压为450 V，负载为30 Ω时，脉冲电流13 A，前沿20 ns，平顶约80 ns；用3个单元调制器感应叠加，当电容充电电压为450 A，负载为30 Ω时，脉冲电流强度为40 A，前沿25 ns，平顶约70 ns。

Experimental study on MOSFET pulse modulator

The design of the trigger based on complex programmable logic device(CPLD), the driver circuit and the residual current device(RCD) circuit of MOSFET pulse modulator were introduced, and the parallel-switch and inductive-adder MOSFET modulators were experimentally studied. The push-pull output circuit made up of a pair of MOSFETs was used in the driver circuit. The Pspice simulation results indicated that the peak inverse voltage on MOSFET switch could be clamped by RCD. A pulse current with an amplitude of 13 A, a rise time of 20 ns and a flat top time of 80 ns was obtained on the load of 30 Ω when 3 parallel MOSFET modulator was adopted as the switch and the charge voltage was 450 V, while the amplitude of the obtained pulse was 40 A, the rise time 25 ns and flat top time 70 ns on the l