Relationship of annealing time and intrinsic defects of unintentionally doped 4H-SiC

With annealing temperature kept at 1573 K, the effects of annealing time on stability of the intrinsic defects in epitaxial unintentionally doped 4H-SiC prepared by low pressure chemical vapour deposition have been studied by electron spin resonance (ESR) and low temperature photoluminescence. This paper reports the results shown that annealing time has an important effect on the intrinsic defects in unintentionally doped 4H-SiC when annealing temperature kept at 1573 K. When the annealing time is less than 30 min, the intensity of ESR and photoluminescence is increasing with annealing time prolonged, and reaches the maximum when annealing time is 30 min. Then the intensity of ESR and photoluminescence is rapidly decreased with the longer annealing time, and much less than that of as-grown 4H-SiC when annealing time is 60 min, which should be related with the interaction among the intrinsic defects during the annealing process.     

SiC晶体缺陷的阴极荧光无损表征研究

由于在研究SiC晶体缺陷对器件性能的影响的过程中,表征材料缺陷的常用的方法是破坏性的,因此寻找一种无损的测试方法对缺陷进行有效的表征显得尤为重要。基于阴极荧光(CL)的工作原理对4H-SiC同质外延材料的晶体缺陷进行了无损测试研究。结果发现利用阴极荧光可以观测到晶体内部的堆垛层错、刃位错和螺位错以及基面位错,其阴极荧光图中的形貌分别为直角三角形、点状和短棒状。因此该方法成为SiC晶体缺陷的无损表征时的一种有效的测试方法。如果利用该方法对材料的衬底和外延层缺陷分别进行观测就能建立起衬底和外延层缺陷之间的某种联系,另外对器件工作前后的缺陷进行表征,建立器件工作前后缺陷之间的联系,就可以进一步地研究材料缺陷对器件性能影响的问题。     

Characterization of ion-implanted 4H-SiC Schottky barrier diodes

Ion-implantation layers are fabricated by multiple nitrogen ion-implantations (3 times for sample A and 4 times for sample B) into a p-type 4H-SiC epitaxial layer. The implantation depth profiles are calculated by using the Monte Carlo simulator TRIM. The fabrication process and the I--V and C--V characteristics of the lateral Ti/4H-SiC Schottky barrier diodes (SBDs) fabricated on these multiple box-like ion-implantation layers are presented in detail. Measurements of the reverse I--V characteristics demonstrate a low reverse current, which is good enough for many SiC-based devices such as SiC metal--semiconductor field-effect transistors (MESFETs), and SiC static induction transistors (SITs). The parameters of the diodes are extracted from the forward I--V and C--V characteristics. The values of ideality factor n of SBDs for samples A and B are 3.0 and 3.5 respectively, and the values of series resistance R_\rm s are 11.9 and 1.0~kΩ respectively. The values of barrier height φ _\rm B of Ti/4H-SiC are 0.95 and 0.72 eV obtained by the I--V method and 1.14 and 0.93 eV obtained by the C--V method for samples A and B respectively. The activation rates for the implanted nitrogen ions of samples A and B are 2\% and 4\% respectively extracted from C--V testing results.     

功率AlGaAs/GaAs HBT自加热频率特性

提出了一种功率AlGaAs/GaAs HBT的自加热温度模型,讨论了在大电流条件下,器件晶格温度升高和基区扩展效应对HBT器件频率特性的影响,并对器件的晶格温度、截止频率和最高振荡频率在自加热条件下的变化分别进行了计算和模拟.     

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor(TFET) is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional(2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.     

0.15-μm T-gate In_(0.52)Al_(0.48)As/In_(0.53)Ga_(0.47)As InP-based HEMT with fmax of 390 GHz

In this paper, 0.15-μm gate-length In0.52Al0.48As/In0.53Ga0.47As InP-based high electron mobility transistors （HEMTs） each with a gate-width of 2×50 μm are designed and fabricated. Their excellent DC and RF characterizations are demonstrated. Their full channel currents and extrinsic maximum transconductance （gm,max） values are measured to be 681 mA/mm and 952 mS/mm, respectively. The off-state gate-to-drain breakdown voltage （BVGD） defined at a gate current of-1 mA/mm is 2.85 V. Additionally, a current-gain cut-off frequency （fT） of 164 GHz and a maximum oscillation frequency （fmax） of 390 GHz are successfully obtained; moreover, the fmax of our device is one of the highest values in the reported 0.15-μm gate-length lattice-matched InP-based HEMTs operating in a millimeter wave frequency range. The high gm,max, BVGD, fmax, and channel current collectively make this device a good candidate for high frequency power applications.     

应变Si NMOS积累区电容特性研究

积累区MOS电容线性度高且不受频率限制, 具有反型区MOS电容不可比拟的优势. 本文在研究应变Si NMOS电容C-V特性中台阶效应形成机理的基础上, 通过求解电荷分布, 建立了应变Si/SiGe NMOS积累区电容模型, 并与实验结果进行了对比, 验证了模型的正确性. 最后, 基于该模型, 研究了锗组分、应变层厚度、掺杂浓度等参数对台阶效应的影响, 为应变Si器件的制造提供了重要的指导作用. 本模型已成功用于硅基应变器件模型参数提取软件中, 为器件仿真奠定了理论基础. 关键词： 应变Si NMOS 积累区电容 台阶效应 电荷分布     

斜抽运无机液体激光器的流场热分布

激光二极管斜抽运的多增益段串接的液体激光器能够明显地提高激光光束质量、获得较高的输出功率.针对斜抽运子增益段工作时所涉及的流动、传热和壁面耦合,建立了计算子增益段流场热分布的流-热-固耦合模型,应用有限单元法完成了其瞬态流场热分布的数值模拟.该方法排除了不精确的换热系数对计算结果的影响,使得换热系数不再是计算的先决条件,而只是计算结果之一,并且为评价流道形状、流速、吸收系数等因素对流场热的影响,以及进一步改进和控制液体激光介质的流场热分布,提供了可靠的分析方法.数值模拟研究表明:换热系数是空间位置的函数,     

Temperature-dependent characteristics of 4Hben SiC junction barrier Schottky diodes

The current-voltage characteristics of 4H-SiC junction barrier Schottky (JBS) diodes terminated by an offset field plate have been measured in the temperature range of 25-300 ℃. An experimental barrier height value of about 0.5 eV is obtained for the Ti/4H-SiC JBS diodes at room temperature. A decrease in the experimental barrier height and an increase in the ideality factor with decreasing temperature are shown. Reverse recovery testing also shows the temperature dependence of the peak recovery current density and the reverse recovery time. Finally, a discussion of reducing the reverse recovery time is presented.     

Investigation of a 4H-SiC metal-insulation-semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited(ALD) Al2O3 /dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8°off-axis 4H-SiC(0001) epitaxial wafers are investigated in this paper.The metal-insulation-semiconductor(MIS) capacitors,respectively with different gate dielectric stacks(Al2O3/SiO2,Al2O3,and SiO2) are fabricated and compared with each other.The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field(≥12 MV/cm) comparable to SiO2,and a relatively low gate leakage current of1×10-7A/cm2 at an electric field of4 MV/cm comparable to Al2O3.The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage,indicating a less effective charge and slow-trap density near the interface.