Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-k gate dielectric

By solving Poisson＇s equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate （DMSG） metal-oxide semiconductor field-effect transistor （MOSFET） with a high-k gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering （FIBL） on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.     

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high-κ insulator

An improved vertical power double-diffused metal–oxide–semiconductor(DMOS) device with a p-region(P1) and high-κ insulator vertical double-diffusion metal–oxide–semiconductor(HKP-VDMOS) is proposed to achieve a better performance on breakdown voltage(BV)/specific on-resistance(Ron,sp) than conventional VDMOS with a high-κ insulator(CHK-VDMOS).The main mechanism is that with the introduction of the P-region,an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage.Due to the assisted depletion effect of this p-region,the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region.Meanwhile,based on the superposition of the depleted charges,a closed-form model for electric field/breakdown voltage is generally derived,which is in good agreement with the simulation result within 10% of error.An HKP-VDMOS device with a breakdown voltage of 600 V,a reduced specific on-resistance of 11.5 m?·cm~2 and a figure of merit(FOM)(BV~2/Ron,sp)of 31.2 MW·cm~(-2) shows a substantial improvement compared with the CHK-VDMOS device.     

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.     

Modeling of high permittivity insulator structure with interface charge by charge compensation

An analytical model of the power metal–oxide–semiconductor field-effect transistor(MOSFET)with high permittivity insulator structure(HKMOS)with interface charge is established based on superposition and developed for optimization by charge compensation.In light of charge compensation,the disturbance aroused by interface charge is efficiently compromised by introducing extra charge for maximizing breakdown voltage(BV)and minimizing specific ON-resistance(R_on,sp).From this optimization method,it is very efficient to obtain the design parameters to overcome the difficulty in implementing the R_on,sp–BV trade-off for quick design.The analytical results prove that in the HKMOS with positive or negative interface charge at a given length of drift region,the extraction of the parameters is qualitatively and quantitatively optimized for trading off BV and Ron,sp with JFET effect taken into account.     

Low-Frequency Noise in Amorphous Indium Zinc Oxide Thin Film Transistors with Aluminum Oxide Gate Insulator

Low-frequency noise(LFN) in all operation regions of amorphous indium zinc oxide(a-IZO) thin film transistors(TFTs) with an aluminum oxide gate insulator is investigated. Based on the LFN measured results, we extract the distribution of localized states in the band gap and the spatial distribution of border traps in the gate dielectric,and study the dependence of measured noise on the characteristic temperature of localized states for a-IZO TFTs with Al_2 O_3 gate dielectric. Further study on the LFN measured results shows that the gate voltage dependent noise data closely obey the mobility fluctuation model, and the average Hooge's parameter is about 1.18×10~(-3).Considering the relationship between the free carrier number and the field effect mobility, we simulate the LFN using the △N-△μ model, and the total trap density near the IZO/oxide interface is about 1.23×10~(18) cm~(-3)eV~(-1).     

Effect of interface-roughness scattering on mobility degradation in SiGe p-MOSFETs with a high-k dielectric/SiO2 gate stack＊

A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.     

Performance Improvement of Organic Thin Film Transistors Based on Gate Insulator Polymethyl-Methacrylate-co-Glyciclyl-Methacrylate

Organic thin transistors （OTFTs） on indium tin oxide glass substrates are prepared with polymethyl-methacrylate-co-glyciclyl-methacrylate （PMMA-GMA） as the gate insulator layer and copper phthalocyanine as the organic semiconductor layer. By controlling the thickness, the average roughness of surface is reduced and the OTFT performance is improved with leak current decreasing to 10^-11 A and on/off ratio of 10^4. Under the condition of drain-source voltage -20 V, a threshold voltage of -3.5 V is obtained. The experimental results show that PMMA-GMA is a promising insulator material with a dielectric constant in a range of 3.9-5.0.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

High-Mobility P-Type MOSFETs with Integrated Strained-Si_(0.73)Ge_(0.27) Channels and High-κ/Metal Gates

Strained-Si_(0.73)Ge_(0.27) channels are successfully integrated with high-κ/metal gates in p-type metal-oxide- semiconductor field effect transistors(pMOSFETs) using the replacement post-gate process.A silicon cap and oxide inter layers are inserted between Si_(0.73)Ge_(0.27) and high-κ dielectric to improve the interface.The fabricated Si_(0.73) Ge_(0.27) pMOSFETs with gate length of 30 nm exhibit good performance with high drive current(~428μA/μm at V_(DD) = 1 V) and suppressed short-channel effects(DIBL~77mV/V and SS~90mV/decade).It is found that the enhancement of effective hole mobility is up to 200%in long-gate-length Si_(0.73) Ge_(0.27)-channel pMOSFETs compared with the corresponding silicon transistors.The improvement of device performance is reduced due to strain relaxation as the gate length decreases,while 26%increase of the drive current is still obtained for 30-nm-gate-length Si_(0.73)Ge_(0.27) devices.     

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.     

A threshold voltage model MOSFETs considering for high-k gate-dielectric fringing-field effect

In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.     

Ferroelectric effect and equivalent polarization charge model of PbZr_(0.2)Ti_(0.8)O_3 on AlGaN/GaN MIS-HEMT

PbZr_(0.2)Ti_(0.8)O_3(PZT) gate insulator with the thickness of 30 nm is grown by pulsed laser deposition(PLD) in AlGa N/Ga N metal–insulator–semiconductor high electron mobility transistors(MIS-HEMTs). The ferroelectric effect of PZT Al Ga N/Ga N MIS-HEMT is demonstrated. The polarization charge in PZT varies with different gate voltages. The equivalent polarization charge model(EPCM) is proposed for calculating the polarization charge and the concentration of two-dimensional electron gas(2 DEG). The threshold voltage(Vth) and output current density(IDS) can also be obtained by the EPCM. The theoretical values are in good agreement with the experimental results and the model can provide a guide for the design of the PZT MIS-HEMT. The polarization charges of PZT can be modulated by different gate-voltage stresses and the Vthhas a regulation range of 4.0 V. The polarization charge changes after the stress of gate voltage for several seconds. When the gate voltage is stable or changes at high frequency, the output characteristics and the current collapse of the device remain stable.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

Effect of overdrive voltage on PBTI trapping behavior in GaN MIS-HEMT with LPCVD SiNx gate dielectric

The effect of high overdrive voltage on the positive bias temperature instability(PBTI)trapping behavior is investigated for GaN metal–insulator–semiconductor high electron mobility transistor(MIS-HEMT)with LPCVD-SiNx gate dielectric.A higher overdrive voltage is more effective to accelerate the electrons trapping process,resulting in a unique trapping behavior,i.e.,a larger threshold voltage shift with a weaker time dependence and a weaker temperature dependence.Combining the degradation of electrical parameters with the frequency–conductance measurements,the unique trapping behavior is ascribed to the defect energy profile inside the gate dielectric changing with stress time,new interface/border traps with a broad distribution above the channel Fermi level are introduced by high overdrive voltage.     

Improvement in electrical properties of high-κ film on Ge substrate by an improved stress relieved pre-oxide method

High-κ /Ge gate stack has recently attracted a great deal of attention as a potential candidate to replace planar silicon transistors for sub-22 generation. However, the desorption and volatilization of GeO hamper the development of Ge-based devices. To cope with this challenge, various techniques have been proposed to improve the high-κ /Ge interface. However,these techniques have not been developed perfectly yet to control the interface. Therefore, in this paper, we propose an improved stress relieved pre-oxide(SRPO) method to improve the thermodynamic stability of the high-κ /Ge interface. The x-ray photoelectron spectroscopy(XPS) and atomic force microscopy(AFM) results indicate that the GeO volatilization of the high-κ /Ge gate stack is efficiently suppressed after 500℃ annealing, and the electrical characteristics are greatly improved.     

Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

Based on the quasi-two-dimensional(2D) solution of Poisson’s equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate(JLDMCSG) metal-oxide-semiconductor field-effect transistor(MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG(JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage rolloff of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional(3D) numerical device simulator ISE.     

A 3D SiC MOSFET with poly-silicon/SiC heterojunction diode

A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively.     

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer(BOX)(DGRD MOSFET).First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage(BV).The BV of 233 V and Ron,sp of 4.151 mΩ·cm2(VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.     

Valence band variation in Si (110) nanowire induced by a covered insulator

In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a generalized 6 × 6k$\cdot$p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO₂ insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO₂ insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO₂ insulator, the strain of the HfO₂ gate insulator in Si (110) nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO₂ insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design.     

Synthesis of thermally stable HfO_xN_y as gate dielectric for AlGaN/GaN heterostructure field-effect transistors

In this paper, we adopted thermally stable HfO_xN_y as gate dielectric for TiN/HfO_xN_y/AlGaN/GaN heterostructure field-effect transistors(HFETs) application. It demonstrated that the surface morphologies, composition, and optical properties of the HfO_xN_y films were dependent on oxygen flow rate in the O_2/N_2/Ar mixture sputtering ambient. The obtained metal–oxide–semiconductor heterostructure field-effect transistors by depositing HfO_2 and HfO_xN_y dielectric at different oxygen flow rates possessed a small hysteresis and a low leakage current. After post deposition annealing at 900℃, the device using HfO_xN_y dielectric operated normally with good pinch-off characteristics, while obvious degradation are observed for the HfO_2 gated one at 600℃. This result shows that the HfO_xN_y dielectric is a promising candidate for the self-aligned gate process.