共查询到20条相似文献,搜索用时 546 毫秒
1.
Hot-carrier degradation for 90 nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4 nm) gate oxide is investigated under the low gate voltage stress (LGVS) and peak substrate current (Isub max) stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage (GIDL) current and stress induced leakage current (SILC). The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses. 相似文献
2.
A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures 下载免费PDF全文
We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper. 相似文献
3.
实验结果发现突发击穿(snapback),偏置下雪崩热空穴注入NMOSFET栅氧化层,产生界面态,同时空穴会陷落在氧化层中.由于栅氧化层很薄,陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱,使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电,引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段:第一阶段亚阈值电流是主要成分,第二阶段栅电流是主要成分.在预加热电子(HE)应力后,HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层,使器件snapback开态和关态特性退化变小.
关键词:
突发击穿
软击穿
应力引起的泄漏电流
热电子应力 相似文献
4.
本文研究了90nm CMOS工艺下栅氧化层厚度为1.4 nm沟道长度为100 nm的轻掺杂漏(LDD)nMOSFET栅电压VG对栅致漏极泄漏 (GIDL)电流Id的影响,发现不同VG下ln (Id/(VDG-1.2))-1/(VDG-1.2)曲线相比大尺寸厚栅器件时发生了分裂现象. 通过比较VG变化下ln(Id/(VDG-1.2))的差值,得出VG与这种分裂现象之间的作用机理,分裂现象的产生归因于VG的改变影响了GIDL电流横向空穴隧穿部分所致. 随着|VG|的变小,ln(Id/(VDG-1.2))曲线的斜率的绝对值变小.进一步发现不同VG对应的ln (Id/(VDG-1.2))曲线的斜率c及截距d与VG呈线性关系,c,d曲线的斜率分别为3.09和-0.77. c与d定量的体现了超薄栅超短沟器件中VG对GIDL电流的影响,基于此,提出了一个引入VG 影响的新GIDL电流关系式. 相似文献
5.
对1.4nm超薄栅LDD nMOSFET器件栅致漏极泄漏GIDL(gate-induced drain leakage)应力下的阈值电压退化进行了研究.GIDL应力中热空穴注进LDD区界面处并产生界面态,这导致器件的阈值电压变大.相同栅漏电压VDG下的不同GIDL应力后阈值电压退化量的对数与应力VD/VDG的比值成正比.漏偏压VD不变的不同GIDL应力后阈值电压退化随着应力中栅电压的增大而增大,相同栅偏压VG下的不同GIDL应力后阈值电压退化也随着应力中漏电压的增大而增大,这两种应力情形下退化量在半对数坐标下与应力中变化的电压的倒数成线性关系,它们退化斜率的绝对值分别为0.76和13.5.实验发现器件退化随着应力过程中的漏电压变化远大于随着应力过程中栅电压的变化.
关键词:
栅致漏极泄漏
CMOS
阈值电压
栅漏电压 相似文献
6.
Actions of negative bias temperature instability (NBTI) and hot carriers in ultra-deep submicron p-channel metal——oxide——semiconductor field-effect transistors (PMOSFETs) 下载免费PDF全文
Hot carrier injection (HCI) at high temperatures and different
values of gate bias Vg has been performed in order to study
the actions of negative bias temperature instability (NBTI) and hot
carriers. Hot-carrier-stress-induced damage at Vg=Vd, where Vd is the voltage of the transistor drain,
increases as temperature rises, contrary to conventional hot carrier
behaviour, which is identified as being related to the NBTI. A
comparison between the actions of NBTI and hot carriers at low and
high gate voltages shows that the damage behaviours are quite
different: the low gate voltage stress results in an increase in
transconductance, while the NBTI-dominated high gate voltage and
high temperature stress causes a decrease in transconductance. It is
concluded that this can be a major source of hot carrier damage at
elevated temperatures and high gate voltage stressing of p-channel
metal--oxide--semiconductor field-effect transistors (PMOSFETs). We
demonstrate a novel mode of NBTI-enhanced hot carrier degradation in
PMOSFETs. A novel method to decouple the actions of NBTI from that
of hot carriers is also presented. 相似文献
7.
采用不同的高场应力和栅应力对AlGaN/GaN HEMT器件进行直流应力测试,实验发现:应力后器件主要参数如饱和漏电流,跨导峰值和阈值电压等均发生了明显退化,而且这些退化还是可以完全恢复的;高场应力下,器件特性的退化随高场应力偏置电压的增加和应力时间的累积而增大;对于不同的栅应力,相对来说,脉冲栅应力和开态栅应力下器件特性的退化比关态栅应力下的退化大.对不同应力前后器件饱和漏电流,跨导峰值和阈值电压的分析表明,AlGaN势垒层陷阱俘获沟道热电子以及栅极电子在栅漏间电场的作用下填充虚栅中的表面态是这些不同应
关键词:
AlGaN/GaN HEMT器件
表面态(虚栅)
势垒层陷阱
应力 相似文献
8.
研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性,包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性,分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起,同时还有电子的翻越和渗透.在电压应力下,SiO2中形成的缺陷不仅降低了SiO2的势垒高度,而且等效减小了SiO2的厚度(势垒宽度).另外,每一个缺陷都会形成一个导电通道,这些导电通道的形成增大了栅电流,导致器件性能的退化,同时栅击穿时间变长.
关键词:
超薄栅氧化层
斜坡电压
经时击穿
渗透 相似文献
9.
In this paper, we propose a novel Schottky barrier MOSFET structure,
in which the silicide source/drain is designed on the buried metal
(SSDOM). The source/drain region consists of two layers of silicide
materials. Two Schottky barriers are formed between the silicide
layers and the silicon channel. In the device design, the top barrier
is lower and the bottom is higher. The lower top contact barrier is
to provide higher {on-state} current, and the higher bottom contact
barrier to reduce the off-state current. To achieve this, ErSi is
proposed for the top silicide and CoSi2 for the bottom in the
n-channel case. The 50~nm n-channel SSDOM is thus simulated to
analyse the performance of the SSDOM device. In the simulations, the
top contact barrier is 0.2e~V (for ErSi) and the bottom barrier is
0.6eV (for CoSi2. Compared with the corresponding conventional
Schottky barrier MOSFET structures (CSB), the high on-state
current of the SSDOM is maintained, and the off-state current is
efficiently reduced. Thus, the high drive ability (1.2mA/μm
at Vds=1V,
Vgs=2V) and the high Ion/Imin ratio (106)
are both achieved by applying the SSDOM
structure. 相似文献
10.
研究了恒压应力下超薄栅氧化层n型金属-氧化物-半导体场效应晶体管(n-MOSFET)软击穿 后的导电机制.发现在一定的栅电压Vg范围内,软击穿后的栅电流Ig符合Fowl er-Nordheim隧穿公式,但室温下隧穿势垒b的平均值仅为0936eV,远小于S i/Si O2界面的势垒高度315eV.研究表明,软击穿后,处于Si/SiO2界 面量子化能级上的 电子不隧穿到氧化层的导带,而是隧穿到氧化层内的缺陷带上.b与缺陷带能 级和电 子所处的量子能级相关;高温下,激发态电子对隧穿电流贡献的增大导致b逐 渐降低.
关键词:
软击穿
栅电流
类Fowler-Nordheim隧穿
超薄栅氧化层 相似文献
11.
A low specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce Ron,sp and maintain a high breakdown voltage (BV). The BV of 233 V and Ron,sp of 4.151 mΩ·cm2 (VGS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. 相似文献
12.
对65 nm互补金属氧化物半导体工艺下不同尺寸的N型和P型金属氧化物半导体场效应晶体管(NMOSFET和PMOSFET)开展了不同偏置条件下电离总剂量辐照实验.结果表明:PMOSFET的电离辐射响应与器件结构和偏置条件均有很强的依赖性,而NMOSFET表现出较强的抗总剂量性能;在累积相同总剂量时,PMOSFET的辐照损伤远大于NMOSFET.结合理论分析和数值模拟给出了PMOSFET的辐射敏感位置及辐射损伤的物理机制. 相似文献
13.
Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor 下载免费PDF全文
This paper studies the effect of drain bias on
ultra-short p-channel metal-oxide-semiconductor field-effect
transistor (PMOSFET) degradation during negative bias temperature
(NBT) stress. When a relatively large gate voltage is applied, the
degradation magnitude is much more than the drain voltage which is
the same as the gate voltage supplied, and the time exponent gets
larger than that of the NBT instability (NBTI). With decreasing
drain voltage, the degradation magnitude and the time exponent all
get smaller. At some values of the drain voltage, the degradation
magnitude is even smaller than that of NBTI, and when the drain
voltage gets small enough, the exhibition of degradation becomes
very similar to the NBTI degradation. When a relatively large drain
voltage is applied, with decreasing gate voltage, the
degradation magnitude gets smaller. However, the time exponent
becomes larger. With the help of electric field simulation, this
paper concludes that the degradation magnitude is determined by the
vertical electric field of the oxide, the amount of hot holes
generated by the strong channel lateral electric field at the
gate/drain overlap region, and the time exponent is mainly
controlled by localized damage caused by the lateral electric
field of the oxide in the gate/drain overlap region where hot carriers
are produced. 相似文献
14.
Jakub Kedzierski Peiqi Xuan Vivek Subramanian Jeffrey Bokor Tsu-Jae King Chenming Hu Erik Anderson 《Superlattices and Microstructures》2000,28(5-6)
As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 μ A μ m − 1on-current and on/off current ratios of 106, for a conservative oxide thickness of 40 Å and | Vg − Vt| = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in | Vt| is obtained in devices with gate lengths ranging from 100 to 20 nm. 相似文献
15.
Comparison of hot-hole injections in ultrashort channel LDD nMOSFETs with ultrathin oxide under an alternating stress 下载免费PDF全文
The behaviours of three types of hot-hole injections in ultrashort
channel lightly doped drain (LDD) nMOSFETs with ultrathin oxide
under an alternating stress have been compared. The three types of
hot-hole injections, i.e. low gate voltage hot hole injection
(LGVHHI), gate-induced drain leakage induced hot-hole injection
(GIDLIHHI) and substrate hot-hole injection (SHHI), have different
influences on the devices damaged already by the previous hot
electron injection (HEI) because of the different locations of
trapping holes and interface states induced by the three types of
injections, i.e. three types of stresses. Experimental results show
that GIDLIHHI and LGVHHI cannot recover the degradation of electron
trapping, but SHHI can. Although SHHI can recover the device's
performance, the recovery is slight and reaches saturation quickly,
which is suggested here to be attributed to the fact that trapped
holes are too few and the equilibrium is reached between the
trapping and releasing of holes which can be set up quickly in the
ultrathin oxide. 相似文献
16.
Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature 下载免费PDF全文
This paper studies the degradation of device parameters
and that of stress induced leakage current (SILC) of thin tunnel
gate oxide under channel hot electron (CHE) stress at high
temperature by using n-channel metal oxide semiconductor field
effect transistors (NMOSFETs) with 1.4-nm gate oxides. The
degradation of device parameters under CHE stress exhibits
saturating time dependence at high temperature. The emphasis of this
paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high
temperature. Based on the experimental results, it is found that
there is a linear correlation between SILC degradation and Vh
degradation in NMOSFETs during CHE stress. A model of
the combined effect of oxide trapped negative charges and interface
traps is developed to explain the origin of SILC during CHE stress. 相似文献
17.
18.
H.Y. Yu D.S. Lee S.S. Kim B. Kim S.W. Lee J.G. Park S.H. Lee G.C. McIntosh Y.W. Park M.S. Kabir E.E.B. Campbell S. Roth 《Applied Physics A: Materials Science & Processing》2004,79(7):1613-1615
We investigated the current–voltage characteristics of a carbon nanotube in a single electron transistor structure with alternating gate voltage. A continuous current enhancement effect with increasing frequency of the applied gate voltage up to 13 MHz is reported. Assuming that I=nef, more than 1000 electrons are driven to flow across the source–drain channel at VDS=100 mV, 13 MHz of gate voltage (Vp-p=2 V) and T=1.8 K. The continuous current enhancement is explained by the broadening effect of the discrete energy levels of the finite-length carbon nanotube. PACS 61.46.+w; 73.23.Hk; 73.63.Fg; 81.07.De; 85.35.Kt 相似文献
19.
用斜坡电压法(Voltage Ramp, V-ramp)评价了0.18μm双栅极 CMOS工艺栅极氧化膜击穿电量(Charge to Breakdown, Qbd)和击穿电压(Voltage to Breakdown, Vbd). 研究结果表明,低压器件(1.8V)的栅极氧化膜(薄氧)p型衬底MOS电容和N型衬底电容的击穿电量值相差较小,而高压器件(3.3V)栅极氧化膜(厚氧)p衬底MOS电容和n衬底MOS电容的击穿电量值相差较大,击穿电压测试值也发现与击穿电量
关键词:
薄氧
可靠性
击穿电压
击穿电量 相似文献
20.
The NBTI degradation phenomenon and the role of hydrogen during NBT stress
are presented in this paper. It is found that PBT stress can recover a
fraction of Vth shift induced by NBTI. However, this recovery is
unstable. The original degradation reappears soon after reapplication of the NBT
stress condition. Hydrogen-related species play a key role during a device's NBT
degradation. Experimental results show that the diffusion species are
neutral, they repassivate Si dangling bond which is independent of the gate
voltage polarity. In addition to the diffusion towards gate oxide, hydrogen
diffusion to Si-substrate must be taken into account for it also has
important influence on device degradation during NBT stress. 相似文献