低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

Study on characteristics of a double-conductible channel organic thin-films transistor with an ultra-thin hole-blocking layer

The properties of top-contact organic thin-film transistors (TC-OTFTs) using ultra-thin 2, 9-dimethyl-4, 7-diphenyl-1, 10-phenanthroline (BCP) as a hole-blocking interlayer have been improved significantly and a BCP interlayer was inserted into the middle of the pentacene active layer. This paper obtains a fire-new transport mode of an OTFT device with double-conductible channels. The accumulation and transfer of the hole carriers are limited by the BCP interlayer in the vertical region of the channel. A huge amount of carriers is located not only at the interface between pentacene and the gate insulator, but also at the two interfaces of pentacene/BCP interlayer and pentacene/gate insulator, respectively. The results suggest that the BCP interlayer may be useful to adjust the hole accumulation and transfer, and can increase the hole mobility and output current of OTFTs. The TC-OTFTs with a BCP interlayer at V_DS=-20~V showed excellent hole mobility μ_FE and threshold voltage V_TH of 0.58~cm²/(V\cdots) and --4.6~V, respectively.     

The fabrication and characterization of 4H SiC power UMOSFETs

The fabrication of 4H-SiC vertical trench-gate metal-oxide-semiconductor field-effect transistors(UMOSFETs) is reported in this paper.The device has a 15-μm thick drift layer with 3×1015 cm-3 N-type doping concentration and a 3.1μm channel length.The measured on-state source-drain current density is 65.4 A/cm2 at Vg = 40 V and VDS = 15 V.The measured threshold voltage(Vth) is 5.5 V by linear extrapolation from the transfer characteristics.A specific on-resistance(Rsp-on) is 181 mΩ·cm2 at Vg = 40 V and a blocking voltage(BV) is 880 V(IDS = 100 μA@880V) at Vg = 0 V.     

Surface modified polymeric gate insulators for pentacene organic thin-film transistors

This paper demonstrates effects of a surface modification of polymeric gate insulators on a performance of organic thin-film transistor (OTFT). Pentacene OTFTs were fabricated with three types of polymer gate insulators—poly(4-vinylphenol) (PVP, G1) with comparably high dielectric constant, polyimide (PI, G2) with n-octadecyl (C₁₈) side chain, which resulted in hydrophobicity and low dielectric constant, and surface modified PVP(G3). The G3 was prepared by a spin-coating the solution of G2 onto the G1 film. We found that the n-octadecyl group of the G3 protruded from the surface and made the PVP surface more hydrophobic. The less polar surface strongly improved the device performance. Subthreshold slope (s.s.) of the OTFT with G3 as the gate insulator decreased significantly to 2.7 V/dec, which was much smaller than that of OTFTs fabricated with G1 (4.0 V/dec). That is, thin layer with fewer C₁₈ group in contact with pentacene induced a good electrical property like lower s.s. Further the higher dielectric constant of the underlying layer resulted in higher mobility of the device. The mobility (0.50 cm² V⁻¹ s⁻¹) of the OTFT with G3 as the gate insulator showed a higher value compared to that (0.25 cm² V⁻¹ s⁻¹) of the OTFT with G2.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Reduction of the contact resistance in copper phthalocyanine thin film transistor with UV/ozone treated Au electrodes

Bottom-contact (BC) copper phthalocyanine (CuPc) thin film transistor with UV/ozone treated Au as a source/drain electrode was fabricated and the contact resistance was estimated from the transmission line method (TLM). Comparing the properties of OTFT with untreated Au electrode, the performance of the BC CuPc-TFT with the UV/ozone treated Au electrodes was significantly improved: saturation mobility increased from 4.69 × 10⁻³ to 2.37 × 10⁻² cm²/V s, threshold voltage reduced from −29.1 to −6.4 V, and threshold swing varied from 5.08 to 2.25 V/decade. The contact resistance of the device with UV/ozone treated Au electrodes was nearly 20 times smaller than that of the device with untreated Au electrodes at the gate voltage of −20 V. This result indicated that using the UV/ozone treated Au electrode is an effective method to reduce the contact resistance. The present BC configuration with UV/ozone treated Au electrodes could be a significant step towards the commercialization of OTFT technology.     

High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Highly stable amorphous indium‐zinc‐oxide thin‐film transistors with back‐channel wet‐etch process

The stabilities of amorphous indium‐zinc‐oxide (IZO) thin film transistors (TFTs) with back‐channel‐etch (BCE) structure are investigated. A molybdenum (Mo) source/drain electrode was deposited on an IZO layer and patterned by hydrogen peroxide (H₂O₂)‐based etchants. Then, after etching the Mo layer, SF₆ plasma with direct plasma mode was employed and optimized to improve the bias stress stability. Scanning electron microscopy and X‐ray photoelectron spectroscopic analysis revealed that the etching residues were removed efficiently by the plasma treatment. The modified BCE‐ TFTs showed only threshold voltage shifts of 0.25 V and –0.20 V under positive/negative bias thermal stress (P/NBTS, V_GS = ±30 V, V_DS = 0 V and T = 60 °C) after 12 hours, respectively. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Model and analysis of drain induced barrier lowering effect for 4H--SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL (drain induced barrier lowering) effect for short channel 4H--SiC metal semiconductor field effect transistors (MESFETs). An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H--SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a (channel length/channel depth) ratio, drain applied voltage V_DS and channel doping concentration N_D, thus providing a good basis for the design and modelling of short channel 4H--SiC MESFETs device.     

High performance IGZO/TiO2 thin film transistors using Y2O3 buffer layers on polycarbonate substrate

In this work, we fabricate IGZO TFT devices on flexible substrate at room temperature. The IGZO/TiO₂ TFT has small subthreshold swing of 0.16 V/dec, but suffers large gate leakage and negative threshold voltage. However, the TiO₂ TFT with Y₂O₃ buffer layers shows improved characteristics including a low threshold voltage of 0.55 V, a small sub-threshold swing of 0.175 V/decade and high field-effect mobility of 43 cm²/Vs. Such good performance can be attributed to the enhanced capacitance density and lowered gate leakage owing to the integration of large band gap Y₂O₃ and low-temperature higher-κ TiO₂.     

Low-voltage-drive and high output current ZnO thin-film transistors with sputtering SiO2 as gate insulator

Low-voltage-drive ZnO thin-film transistors (TFTs) with room-temperature radio frequency magnetron sputtering SiO₂ as the gate insulator were fabricated successfully on the glass substrate. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 4.2 V, a field effect mobility of 11.2 cm²/V s, an on/off ratio of 3.1 × 10⁶ and a subthreshold swing of 0.61 V/dec. The drain current can reach to 1 mA while the gate voltage is only of 12 V and drain voltage of 8 V. The C–V characteristics of a MOS capacitor with the structure of ITO/SiO₂/ZnO/Al was investigated. The carrier concentration N_D in the ZnO active layer was determined, the calculated N_D is 1.81 × 10¹⁶ cm⁻³, which is the typical value of undoped ZnO film used as the channel layer for ZnO-TFT devices. The experiment results show that SiO₂ film is a promising insulator for the low voltage and high drive capability oxide TFTs.     

Low-voltage antimony-doped SnO2 nanowire transparent transistors gated by microporous SiO2-based proton conductors

A battery drivable low-voltage transparent lightly antimony（Sb）-doped SnO2 nanowire electric-double-layer （EDL） field-effect transistor （FET） is fabricated on an ITO glass substrate at room temperature. An ultralow operation voltage of 1 V is obtained on account of an untralarge specific gate capacitance （- 2.14 μF/cm2） directly bound up with mobile ions-induced EDL （sandwiched between the top and bottom electrodes） effect. The transparent FET shows excellent electric characteristics with a field-effect mobility of 54.43 cm2/V. s, current on/off ration of 2 × 104, and subthreshold gate voltage swing （S = dVgs/d（logIds）） of 140 mV/decade. The threshold voltage Yth （0.1 V） is estimated which indicates that the SnO2 namowire transistor operates in an n-type enhanced mode. Such a low-voltage transparent nanowire transistor gated by a microporous SiO2-based solid electrolyte is very promising for battery-powered portable nanoscale sensors.     

Junctionless nanowire transistor fabricated with high mobility Ge channel

The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been proposed as an alternative device for sub‐20‐nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS‐compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an I_ON/I_OFF current ratio of 1.2 × 10³ at V_D = –1 V and drain‐induced‐barrier lowering (DIBL) of 87 mV. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Enhancement-mode AlGaN/GaN high electronic mobility transistors with thin barrier

An enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMTs) was fabricated with 15-nm AlGaN barrier layer. E-mode operation was achieved by using fluorine plasma treatment and post-gate rapid thermal annealing. The thin barrier depletion-HEMTs with a threshold voltage typically around --1.7 V, which is higher than that of the 22-nm barrier depletion-mode HEMTs (--3.5 V). Therefore, the thin barrier is emerging as an excellent candidate to realize the enhancement-mode operation. With 0.6-μ m gate length, the devices treated by fluorine plasma for 150-W RF power at 150 s exhibited a threshold voltage of 1.3 V. The maximum drain current and maximum transconductance are 300 mA/mm, and 177 mS/mm, respectively. Compared with the 22-nm barrier E-mode devices, V_T of the thin barrier HEMTs is much more stable under the gate step-stress.     

High-electric-field-stress-induced degradation of SiN passivated AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistors (HEMTs) are fabricated by employing SiN passivation, this paper investigates the degradation due to the high-electric-field stress. After the stress, a recoverable degradation has been found, consisting of the decrease of saturation drain current I_Dsat, maximal transconductance g_m, and the positive shift of threshold voltage V_TH at high drain-source voltage V_DS. The high-electric-field stress degrades the electric characteristics of AlGaN/GaN HEMTs because the high field increases the electron trapping at the surface and in AlGaN barrier layer. The SiN passivation of AlGaN/GaN HEMTs decreases the surface trapping and 2DEG depletion a little during the high-electric-field stress. After the hot carrier stress with V_DS=20 V and V_GS=0 V applied to the device for 10⁴ sec, the SiN passivation decreases the stress-induced degradation of I_Dsat from 36% to 30%. Both on-state and pulse-state stresses produce comparative decrease of I_Dsat, which shows that although the passivation is effective in suppressing electron trapping in surface states, it does not protect the device from high-electric-field degradation in nature. So passivation in conjunction with other technological solutions like cap layer, prepassivation surface treatments, or field-plate gate to weaken high-electric-field degradation should be adopted.     

对以并五苯和酞菁铜为不同有源层的有机薄膜晶体管特性研究

通过扫描电镜和X射线衍射对SiO₂衬底上生长并五苯和酞菁铜薄膜的表面形貌进行表征,并得到在SiO₂衬底上生长的并五苯薄膜是以岛状结构生长,其大小约为100nm,且薄膜有较好的结晶取向,呈多晶态存在. 酞菁铜薄膜则没有表现出明显的生长机理,其呈非晶态存在. 还对通过掩膜的方法制作得以酞菁铜和并五苯为有源层的顶栅极有机薄膜晶体管的特性进行了研究. 有源层的厚度为40nm,绝缘层SiO₂的厚度为250nm,器件的沟道宽长比(W/关键词： 有机薄膜晶体管 并五苯薄膜 酞菁铜薄膜 μ_EF)')" href="#">场效应迁移率(μ_EF)     

Structural,optical and electrical properties of europium picrate tetraethylene glycol complex as emissive material for OLED

A new europium complex [Eu(Pic)₂(H₂O)(EO4)](Pic)·0.75H₂O was synthesized and used as the emission material for the single layer device structure of ITO/EO4–Eu–Pic/Al, using a spin-coating technique. Study on the optical properties of the [Eu(Pic)₂(H₂O)(EO4)](Pic)·0.75H₂O complex where EO4=tetraethylene glycol and Pic=picrate anion, had to be undertaken before being applicable to the study of an organic light emitting diode (OLED). The electrical property of an OLED using current–voltage (I–V) measurement was also studied. In complex, the Eu(III) ion was coordinated with the EO4 ligand as a pentadentate mode, one water molecule, and with two Pic anions as bidentate and monodentate modes, forming a nine-coordination number. The photoluminescence (PL) spectra of the crystalline complex in the solid state and its thin film showed a hypersensitive peak at 613.5–614.9 nm that assigned to the ⁵D₀→⁷F₂ transition. A narrow band emission from the thin film EO4–Eu–Pic was obtained. The typical semiconductor I–V curve of device ITO/EO4–Eu–Pic/Al showed the threshold and turn on voltages at 1.08 and 4.6 V, respectively. The energy transfer process from the ligand to the Eu(III) ion was discussed by investigating the excitation and PL characteristics. Effect of the picrate anion on the device performance was also studied.     

射频磁控溅射低温制备非晶铟镓锌氧薄膜晶体管

利用射频磁控溅射技术室温制备了铟镓锌氧(IGZO)薄膜,采用X射线衍射(XRD)表征薄膜的晶体结构,原子力显微镜(AFM)观察其表面形貌,分光光度计测量其透光率。结果表明:室温制备的IGZO薄膜为非晶态且薄膜表面均匀平整,可见光透射率大于80%。将室温制备的IGZO薄膜作为有源层,在低温(<200℃)条件下成功地制备了铟镓锌氧薄膜晶体管(a-IGZO TFT),获得的a-IGZO-TFT器件的场效应迁移率大于6.0 cm2.V-1.s-1,开关比约为107,阈值电压为1.2 V,亚阈值摆幅(S)约为0.9 V/dec,偏压应力测试a-IGZO TFT阈值电压随时间向右漂移。     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

有机薄膜晶体管中接触效应的研究

研究了接触效应对有机薄膜晶体管性能的影响.首先在n型重掺杂Si片上制备了以M_OO₃修饰的Al电极为源漏电极的Pentacene基OTFTs(organic thin film transistors),器件场效应迁移率μ_ef达到0.42 cm²/V ·s,阈值电压V_T为-9.16 V,开关比4.7×10³.通过中间探针法,对器件电势分布做了定性判断 关键词： 有机薄膜晶体管 场效应迁移率 接触效应 电荷漂移