时标上动力方程在右局部边值条件下正解的存在性

主要研究时标上二阶动力学方程u~(△△)(t)+λ_p(t)f(t,u(σ(t)))=0在右局部边值条件u(0)=0=u~△(σ(1))下正解的存在性.应用格林函数和锥上Krasnoselskii不动点原理给出其正解存在的充分条件及正解存在的特征值区间.     

High-voltage super-junction lateral double-diffused metal-oxide semiconductor with a partial lightly doped pillar

A novel super-junction lateral double-diffused metal-oxide semiconductor(SJ-LDMOS) with a partial lightly doped P pillar(PD) is proposed.Firstly,the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect.Secondly,the new electric field peak produced by the P/P-junction modulates the surface electric field distribution.Both of these result in a high breakdown voltage(BV).In addition,due to the same conduction paths,the specific on-resistance(R on,sp) of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS.Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20V/μm at a 15μm drift length,resulting in a BV of 300V.     

A low on-resistance buried current path SOI p-channel LDMOS compatible with n-channel LDMOS

A novel low specific on-resistance(R on,sp) silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(pLDMOS) compatible with high voltage(HV) n-channel LDMOS(nLDMOS) is proposed.The pLDMOS is built in the N-type SOI layer with a buried P-type layer acting as a current conduction path in the on-state(BP SOI pLDMOS).Its superior compatibility with the HV nLDMOS and low voltage(LV) complementary metal-oxide semiconductor(CMOS) circuitry which are formed on the N-SOI layer can be obtained.In the off-state the P-buried layer built in the NSOI layer causes multiple depletion and electric field reshaping,leading to an enhanced(reduced) surface field(RESURF) effect.The proposed BP SOI pLDMOS achieves not only an improved breakdown voltage(BV) but also a significantly reduced Ron,sp.The BV of the BP SOI pLDMOS increases to 319 V from 215 V of the conventional SOI pLDMOS at the same half cell pitch of 25 μm,and R on,sp decreases from 157 mΩ·cm2 to 55 mΩ·cm2.Compared with the PW SOI pLDMOS,the BP SOI pLDMOS also reduces the R on,sp by 34% with almost the same BV.     

High-voltage SOI lateral MOSFET with a dual vertical field plate

A new silicon-on-insulator(SOI)power lateral MOSFET with a dual vertical field plate(VFP)in the oxide trench is proposed.The dual VFP modulates the distribution of the electric field in the drift region,which enhances the internal field of the drift region and increases the drift doping concentration of the drift region,resulting in remarkable improvements in breakdown voltage(BV)and specific on-resistance(Ron,sp).The mechanism of the VFP is analyzed and the characteristics of BV and Ron,spare discussed.It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V,and the Ron,sp decreases from 366 m·cm2to 110 m·cm2.     

高纯硅中补偿性杂质的光热电离光谱

首先测量了高纯n型硅样品在接近液氦温度区域内随温度变化的光热电离光谱，确定了硅样品的最佳光热电离温度范围. 在该温度范围内，在有本征带隙光照射条件下，测量了样品的高分辨率光热电离光谱，同时观察到了来自主要浅杂质施主磷以及补偿性杂质硼的正信号. 随后，应用外加磁场，对硼的光热电离光谱进行了研究，发现来自硼的光热电离信号，在外加磁场作用下，发生了由正向负信号的转变. 通过对该现象进行分析讨论，排除了该现象是温度效应的可能，指出普遍用来解释补偿性杂质光热电离响应的Darken模型存在不足，而少数载流子快速复合模     

Adaptive synchronization of chaos in permanent magnet synchronous motors based on passivity theory

An adaptive synchronization control method is proposed for chaotic permanent magnet synchronous motors based on the property of a passive system. We prove that the controller makes the synchronization error system between the driving and the response systems not only passive but also asymptotically stable. The simulation results show that the proposed method is effective and robust against uncertainties in the systemic parameters.     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel lateral double-diffused metal\ben oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage (BV) for an ultra-high-voltage (UHV) high-side thin layer silicon-on-insulator (SOI) p-channel low-density metal-oxide semiconductor (LDMOS). Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state (on-state) BV of the SOI p-channel LDMOS can reach 741 (620) V in the 3-μm-thick buried oxide layer, 50-μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.     

A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching

The ruggedness of a superjunction metal–oxide semiconductor field-effect transistor (MOSFET) under unclamped inductive switching conditions is improved by optimizing the avalanche current path. Inserting a P-island with relatively high doping concentration into the P-column, the avalanche breakdown point is localized. In addition, a trench type P+ contact is designed to shorten the current path. As a consequence, the avalanche current path is located away from the N+ source/P-body junction and the activation of the parasitic transistor can be effectively avoided. To verify the proposed structural mechanism, a two-dimensional (2D) numerical simulation is performed to describe its static and on-state avalanche behaviours, and a method of mixed-mode device and circuit simulation is used to predict its performances under realistic unclamped inductive switching. Simulation shows that the proposed structure can endure a remarkably higher avalanche energy compared with a conventional superjunction MOSFET.     

Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel low-density metal-oxide semiconductor

This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage(BV) for an ultra-high-voltage(UHV) high-side thin layer silicon-on-insulator(SOI) p-channel lateral double-diffused metal-oxide semiconductor(LDMOS).Compared with the conventional simulation method,the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit.The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method.Simulation results show that the off-state(on-state) BV of the SOI p-channel LDMOS can reach 741(620) V in the 3-μm-thick buried oxide layer,50-μm-length drift region,and at 400 V back-gate voltage,enabling the device to be used in a 400 V UHV integrated circuit.     

Adaptive synchronization of chaos in permanent magnet synchronous motors based on passivity theory

An adaptive synchronization control method is proposed for chaotic permanent magnet synchronous motors based on the property of a passive system.We prove that the controller makes the synchronization error system between the driving and the response systems not only passive but also asymptotically stable.The simulation results show that the proposed method is effective and robust against uncertainties in the systemic parameters.