Degradation and breakdown behaviors of SGTs under repetitive unclamped inductive switching avalanche stress

The repetitive unclamped inductive switching (UIS) avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET (C-SGT) and P-ring SGT MOSFETs (P-SGT). It is found that the static and dynamic parameters of both devices show different degrees of degradation. Combining experimental and simulation results, the hot holes trapped into the Si/SiO₂ interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors. Moreover, under repetitive UIS avalanche stress, the reliability of P-SGT overcomes that of C-SGT, benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.     

A novel planar vertical double-diffused metal-oxide- semiconductor field-effect transistor with inhomogeneous floating islands

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R_on,sp), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R_on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R_on,sp are investigated, and the optimized results with BV of 83 V and R_on,sp of 54 mOmega cdotmm² are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior “R_on,sp/BV” trade-off to the conventional VDMOS (a 38% reduction of R_on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R_on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively.     

A 3D SiC MOSFET with poly-silicon/SiC heterojunction diode

A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively.     

A novel photoelectric MOSFET with AC output under constant illumination

Traditional photoelectric devices can generate only DC electric signals under constant illumination. In this work, a novel photoelectric metal-oxide-semiconductor field-effect transistor (MOSFET) with AC output under constant illumination is introduced, in which the channel current is modulated by the gate voltage. This virtue can greatly simplify the signal processing circuitry. This photoelectric MOSFET has been successfully fabricated using a standard 0.8 micron MOSFET process.     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

Study of the multiple-negative-differential-resistance (MNDR) switching behaviors based on heterojunction bipolar transistor (HBT) structures

In this paper, we demonstrate multiple-negative-differential-resistance (MNDR) switching behaviors based on the InGaP/GaAs heterostructure-emitter bipolar transistor (HEBT) and InGaAlAs/InP heterojunction bipolar transistor (HBT) structures. The devices act like conventional HBTs under forward operation mode. The proposed HEBTs show lower offset voltage due to the correct design of the emitter thickness. On the other hand, MNDR phenomena resulting from avalanche multiplication, confinement effects and the potential redistribution process are observed under inverted operation mode for both devices. In addition, three-terminal NDR characteristics are investigated under the applied base currentI_B . Moreover, for the InGaAlAs/InP HBT, anomalous multiple-route and multiple-step current–voltage (I–V) characteristics at 77 K are observed due to the insertion of a InGaAs quantum well (QW) between the base and collector layers.     

Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism

For the first time, we have presented a novel nanoscale fully depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction. The key idea in this work is to suppress the leakage current by injected carriers decrement into the channel from the source in weak inversion regime while we have created a built-in electric field in the channel for improving the on current of device. Therefore, we have introduced a trapezoidal doping that distributed vertically in the channel and called the proposed structure as vertical trapezoid doping fully depleted silicon-on-insulator MOSFET (VTD-SOI). Using two-dimensional two-carrier simulation we demonstrate that the VTD-SOI decreases the leakage current in comparison with conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI). Also, our results show short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement in the proposed structure. Therefore, the VTD-SOI structure shows excellent performance for scaled transistors in comparison with the C-SOI and can be a good candidate for CMOS low power circuits.     

高功率微波作用下金属氧化物半导体场效应管响应

采用基于半导体漂移扩散模型的数值模拟软件对高功率微波(HPM)作用下金属氧化物半导体场效应管(MOSFET)的响应进行了数值模拟研究。对MOSFET在HPM作用下的输出特性以及器件内部响应进行了数值模拟。计算结果表明,在MOSFET栅极加载HPM后,随着注入HPM幅值的增大,会使得器件的正向电压小于开启电压,从而使得输出电流的波形发生形变。在器件内部,导电沟道靠近源极一端的电场强度最大,热量产生集中在这一区域。在脉冲正半周期时,温度峰值位于沟道源极一端,负半周期时,器件内部几乎没有电流,器件内的温度峰值在热扩散效应的影响下趋向于导电沟道中部。     

Sensitivity of heavy-ion-induced single event burnout in SiC MOSFET

The energy deposition and electrothermal behavior of SiC metal-oxide-semiconductor field-effect transistor(MOSFET)under heavy ion radiation are investigated based on Monte Carlo method and TCAD numerical simulation.The Monte Carlo simulation results show that the density of heavy ion-induced energy deposition is the largest in the center of the heavy ion track.The time for energy deposition in SiC is on the order of picoseconds.The TCAD is used to simulate the single event burnout(SEB)sensitivity of SiC MOSFET at four representative incident positions and four incident depths.When heavy ions strike vertically from SiC MOSFET source electrode,the SiC MOSFET has the shortest SEB time and the lowest SEB voltage with respect to direct strike from the epitaxial layer,strike from the channel,and strike from the body diode region.High current and strong electric field simultaneously appear in the local area of SiC MOSFET,resulting in excessive power dissipation,further leading to excessive high lattice temperature.The gate-source junction area and the substrate-epitaxial layer junction area are both the regions where the SiC lattice temperature first reaches the SEB critical temperature.In the SEB simulation of SiC MOSFET at different incident depths,when the incident depth does not exceed the device's epitaxial layer,the heavy-ion-induced charge deposition is not enough to make lattice temperature reach the SEB critical temperature.     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p$+$ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p$+$ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance ($R_{\rm on,sp}$). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage ($V_{\rm BR}$) and $R_{\rm on,sp}$ ($V_{\rm BR}^{2}R_{\rm on,sp}$) of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.     

Terahertz emission from collapsing field domains during switching of a gallium arsenide bipolar transistor

Broadband pulsed THz emission with peak power in the sub-mW range has been observed experimentally during avalanche switching in a gallium arsenide bipolar junction transistor at room temperature, while significantly higher total generated power is predicted in simulations. The emission is attributed to very fast oscillations in the conductivity current across the switching channels, which appear as a result of temporal evolution of the field domains generated in highly dense electron-hole plasma. This plasma is formed in turn by powerful impact ionization in multiple field domains of ultrahigh amplitude.     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.     

New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using a SiGe zone in drift region

High breakdown voltage and reduced on-resistance are desired characteristics in power MOSFETs. In order to obtain an excellent performance of Trench Gate Power MOSFET, we have proposed a new structure in which a SiGe zone is incorporated in the drift region to reduce on-resistance. Also, the buried oxide is considered in the drift region that surrounds the SiGe zone to increase breakdown voltage. The proposed structure is called a SiGe Zone Trench Gate MOSFET (SZ-TG). Our simulation with two dimensional simulator shows that by reducing an electric field and controlling the effects of parasitic BJT transistor in the SZ-TG structure, we can expand power applications of trench gate power structures.     

Comparative simulation of switching regimes of magnetic explosion generators by copper and aluminum magnetodynamic current breakers taking into account elastoplastic properties of materials

We report on the results of the computer simulation of the operation of magnetodynamic break switches used as the second stage of current pulse formation in magnetic explosion generators. The simulation was carried out under the conditions when the magnetic field energy density on the surface of the switching conductor as a function of the current through it was close to but still did not exceed the critical value typical of the beginning of electric explosion. In the computational model, we used the parameters of experimentally tested sample of a coil magnetic explosion generator that can store energy of up to 2.7 MJ in the inductive storage circuit and equipped with a primary explosion stage of the current pulse formation. It has been shown that the choice of the switching conductor material, as well as its elastoplastic properties, considerably affects the breaker speed. Comparative results of computer simulation for copper and aluminum have been considered.     

基于普通三极管电光调Q驱动器的实验研究

利用三极管的雪崩效应获得高电压、快速电光调Q脉冲存在雪崩效应不稳定、输出电压调节范围小、供电电压高等缺点。针对以上不足,采取在三极管基射极加电感使雪崩效应稳定,用高压场效应管替代两个三极管提高输出电压调节范围,利用MarxBank电路,降低供电电压。实验结果表明：电光调Q脉冲前沿2ns,幅度3500-6000V连续可调...     

功率MOSFET的负偏置温度不稳定性效应中的平衡现象

通过对功率金属氧化物半导体场效应晶体管在静态应力下的负偏置温度不稳定性的实验研究, 发现器件参数的退化随时间的关系遵循反应扩散模型所描述的幂函数关系, 并且在不同栅压应力下, 实验结果中均可观察到平台阶段的出现. 基于反应扩散理论的模型进行了仿真研究, 通过仿真结果分析和验证了此平台阶段对应于反应平衡阶段, 并且解释了栅压应力导致平台阶段持续时间不同的原因. 关键词： 功率金属氧化物半导体场效应晶体管 负偏置温度不稳定性 反应扩散模型     

Damage effect and mechanism of the GaAs pseudomorphic high electron mobility transistor induced by the electromagnetic pulse

The damage effect and mechanism of the electromagnetic pulse(EMP) on the GaAs pseudomorphic high electron mobility transistor(PHEMT) are investigated in this paper. By using the device simulation software, the distributions and variations of the electric field, the current density and the temperature are analyzed. The simulation results show that there are three physical effects, i.e., the forward-biased effect of the gate Schottky junction, the avalanche breakdown, and the thermal breakdown of the barrier layer, which influence the device current in the damage process. It is found that the damage position of the device changes with the amplitude of the step voltage pulse. The damage appears under the gate near the drain when the amplitude of the pulse is low, and it also occurs under the gate near the source when the amplitude is sufficiently high, which is consistent with the experimental results.     

单轴应变Si NMOSFET热载流子栅电流模型

热载流子效应产生的栅电流是影响器件功耗及可靠性的重要因素之一,本文基于热载流子形成的物理过程,建立了单轴应变硅NMOSFET热载流子栅电流模型,并对热载流子栅电流与应力强度、沟道掺杂浓度、栅源电压、漏源电压等的关系,以及TDDB(经时击穿)寿命与栅源电压的关系进行了分析研究.结果表明,与体硅器件相比,单轴应变硅MOS器件不仅具有较小的热载流子栅电流,而且可靠性也获得提高.同时模型仿真结果与单轴应变硅NMOSFET的实验结果符合较好,验证了该模型的可行性.     

固态Marx发生器的过流保护研究

具有快速上升沿、低开关损耗的SiC MOSFET已逐渐在固态高压脉冲电源中使用。针对固态Marx发生器中的常见短路故障,分析了SiC MOSFET的过流损坏机制,提出了一种新型的带过流保护的驱动系统。该驱动系统不仅实现了宽驱动信号同步输出,同时能够在整个SiC MOSFET导通期间提供过电流钳制效果。驱动系统中的保护电路利用SiC MOSFET门极电压与漏极电流的关系,通过单个采样电阻和一对反向串联的稳压管将SiC MOSFET门极电压拉低的方式来限制过电流。实验结果表明:当开关管的导通电流较小时,虽然门极电压会有轻微下降,但是SiC MOSFET的导通阻抗仍然很低;而在过电流故障发生时,门极电压会被快速拉低,开关管的导通阻抗急剧上升,从而迅速将导通电流钳制在安全范围内。