A snapback suppressed reverse-conducting IGBT with uniform temperature distribution

A novel reverse-conducting insulated-gate bipolar transistor(RC-IGBT) featuring a floating P-plug is proposed. The P-plug is embedded in the n-buffer layer to obstruct the electron current from flowing directly to the n-collector, which achieves the hole emission from the p-collector at a small collector size and suppresses the snapback effectively. Moreover, the current is uniformly distributed in the whole wafer at both IGBT mode and diode mode, which ensures the high temperature reliability of the RC-IGBT. Additionally, the P-plug acts as the base of the N-buffer/P-float/N-buffer transistor, which can be activated to extract the excessive carriers at the turn-off process. As the the simulation results show, for the proposed RC-IGBT, it achieves almost snapback-free output characteristics with a uniform current density and a uniform temperature distribution, which can greatly increase the reliability of the device.     

A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching

The ruggedness of a superjunction metal–oxide semiconductor field-effect transistor (MOSFET) under unclamped inductive switching conditions is improved by optimizing the avalanche current path. Inserting a P-island with relatively high doping concentration into the P-column, the avalanche breakdown point is localized. In addition, a trench type P+ contact is designed to shorten the current path. As a consequence, the avalanche current path is located away from the N+ source/P-body junction and the activation of the parasitic transistor can be effectively avoided. To verify the proposed structural mechanism, a two-dimensional (2D) numerical simulation is performed to describe its static and on-state avalanche behaviours, and a method of mixed-mode device and circuit simulation is used to predict its performances under realistic unclamped inductive switching. Simulation shows that the proposed structure can endure a remarkably higher avalanche energy compared with a conventional superjunction MOSFET.     

A novel high performance TFS SJ IGBT with a buried oxide layer

A novel high performance trench field stop(TFS) superjunction(SJ) insulated gate bipolar transistor(IGBT) with a buried oxide(BO) layer is proposed in this paper. The BO layer inserted between the P-base and the SJ drift region acts as a barrier layer for the hole-carrier in the drift region. Therefore, conduction modulation in the emitter side of the SJ drift region is enhanced significantly and the carrier distribution in the drift region is optimized for the proposed structure. As a result, compared with the conventional TFS SJ IGBT(Conv-SJ), the proposed BO-SJ IGBT structure possesses a drastically reduced on-state voltage drop(Vce(on)) and an improved tradeoff between Vce(on)and turn-off loss(Eoff), with no breakdown voltage(BV) degraded. The results show that with the spacing between the gate and the BO layer Wo = 0.2 μm, the thickness of the BO layer Lo = 0.2 μm, the thickness of the drift region Ld = 90 μm, the half width and doping concentration of the N- and P-pillars Wn = Wp = 2.5 μm and Nn = Np = 3 × 1015cm-3, the Vce(on)and Eoffof the proposed structure are 1.08 V and 2.81 mJ/cm2with the collector doping concentration Nc = 1×1018cm-3and 1.12 V and1.73 mJ/cm2with Nc = 5 × 1017cm-3, respectively. However, with the same device parameters, the Vce(on)and Eofffor the Conv-SJ are 1.81 V and 2.88 mJ/cm2with Nc = 1 × 1018cm-3and 1.98 V and 2.82 mJ/cm2with Nc = 5 × 1017cm-3,respectively. Meanwhile, the BV of the proposed structure and Conv-SJ are 1414 V and 1413 V, respectively.     

非均匀沟道MOS辐照正空间电荷迁移率模型

提出非均匀沟道MOS辐照正空间电荷迁移率模型.借助镜像法导出沟道电离杂质与辐照正空间电荷的二维场和二维互作用势的分布，由此给出非均匀n沟和p沟的迁移率表示式，其解析解与二维仿真值十分吻合.还借助二维仿真器计算均匀沟道MOS辐照正空间电荷迁移率的变化值，其值和文献［2，3］实验数据一致. 关键词： 非均匀沟道MOS 镜像法 二维互作用势     

Thermal analytic model of current gain for bipolar junction transistor-bipolar static induction transistor compound device

This paper proposes a thermal analytical model of current gain for bipolar junction transistor-bipolar static induction transistor (BJT-BSIT) compound device in the low current operation. It also proposes a best thermal compensating factor to the compound device that indicates the relationship between the thermal variation rate of current gain and device structure. This is important for the design of compound device to be optimized. Finally, the analytical model is found to be in good agreement with numerical simulation and experimental results. The test results demonstrate that thermal variation rate of current gain is below 10% in 25℃--85℃ and 20{\%} in -55℃--25℃.     

A novel planar vertical double-diffused metal-oxide- semiconductor field-effect transistor with inhomogeneous floating islands

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R_on,sp), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R_on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R_on,sp are investigated, and the optimized results with BV of 83 V and R_on,sp of 54 mOmega cdotmm² are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior “R_on,sp/BV” trade-off to the conventional VDMOS (a 38% reduction of R_on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R_on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively.     

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through(LPT) carrier stored trench bipolar transistor(CSTBT) with buried p-layer(BP) is proposed in this paper.Since the negative charges in the BP layer modulate the bulk electric field distribution,the electric field peaks both at the junction of the p base/n-type carrier stored(N-CS) layer and the corners of the trench gates are reduced,and new electric field peaks appear at the junction of the BP layer/N drift region.As a result,the overall electric field in the N drift region is enhanced and the proposed structure improves the breakdown voltage(BV) significantly compared with the LPT CSTBT.Furthermore,the proposed structure breaks the limitation of the doping concentration of the N-CS layer(NN CS) to the BV,and hence a higher NN CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop(Vce(sat)) can be obtained with almost constant BV.The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm-3,a thickness of LBP = 2.5 μm,and a width of WBP = 5 μm,the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V,with NN CS increasing from 5 × 1015 cm-3 to 2.5 × 1016 cm-3.However,with the same N-drift region thickness of 150 μm and NN CS,the BV of the CSTBT decreases from 1598 V to 247 V.Meanwhile,the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN CS increasing from 5 × 1015 cm-3 to 2.5 × 1016 cm-3.