Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator(SOI) devices. In this new structure, the conventional buried oxide(BOX) in an SOI device is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer(NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage(BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor(LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance(Ron,sp) is reduced by 69% in comparison to the conventional structure.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator(SOI) high breakdown voltage(BV) power device with interlaced dielectric trenches(IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges(holes) at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.     

背栅效应对SOI横向高压器件击穿特性的影响

提出一种SOI基背栅体内场降低BG REBULF(back-gate reduced BULk field)耐压技术. 其机理是背栅电压诱生界面电荷，调制有源区电场分布，降低体内漏端电场，提高体内源端电场，从而突破习用结构的纵向耐压限制，提高器件的击穿电压. 借助二维数值仿真，分析背栅效应对厚膜高压SOI LDMOS (>600V) 击穿特性的影响，在背栅电压为330V时，实现器件击穿电压1020V，较习用结构提高47.83%. 该技术的提出，为600V以上级SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路. 关键词： SOI 背栅 体内场降低 LDMOS     

A novel thin drift region device with field limiting rings in substrate

A novel thin drift region device with heavily doped N⁺ rings embedded in the substrate is reported, which is called the field limiting rings in substrate lateral double-diffused MOS transistor (SFLR LDMOS). In the SFLR LDMOS, the peak of the electric field at the main junction is reduced due to the transfer of the voltage from the main junction to other field limiting ring junctions, so the vertical electric field is improved significantly. A model of the breakdown voltage is developed, from which optimal spacing is obtained. The numerical results indicate that the breakdown voltage of the device proposed is increased by 76% in comparison to that of the conventional LDMOS.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n⁺-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n⁺-regions on the interface by the force with ionized donors in the undepleted n⁺-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E_I) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E_I of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.     

Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier: an improved Schottky rectifier with better reverse characteristics

An improved structure of Schottky rectifier,called a trapezoid mesa trench metal-oxide semiconductor (MOS) barrier Schottky rectifier (TM-TMBS),is proposed and studied by two-dimensional numerical simulations.Both forward and especially better reverse I-V characteristics,including lower leakage current and higher breakdown voltage,are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier (TMBS) as well as a conventional planar Schottky barrier diode rectifier.Optimized device parameters corresponding to the requirement for high breakdown voltage are given.With optimized parameters,TM-TMBS attains a breakdown voltage of 186 V,which is 6.3% larger than that of the optimized TMBS,and a leakage current of 4.3×10 6 A/cm 2,which is 26% smaller than that of the optimized TMBS.The relationship between optimized breakdown voltage and some device parameters is studied.Explanations and design rules are given according to this relationship.     

磷化铟复合沟道高电子迁移率晶体管击穿特性研究

用密度梯度量子模型定量研究了磷化铟(InP)复合沟道高电子迁移率晶体管(HEMT)的击穿特性，考虑了复合沟道内碰撞电离以及沟道量子效应，重点研究了器件击穿电压随In_0.7Ga_0.3As沟道厚度的变化关系，提出了提高击穿电压的方法，采用商用器件模拟软件Sentaurus模拟了器件的开态击穿电压，对比了实验和模拟的结果. 研究表明：适当减小In_0.7Ga_0.3As沟道层的厚度可以在保持器件饱和电流基本不变的前提下大幅度提高开态击穿电压，这对于提高InP基HEMT的功率性能具有重要意义. 关键词： 磷化铟 高电子迁移率晶体管 密度梯度模型 击穿     

超结硅锗碳异质结双极晶体管机理研究与特性分析优化

提出一种超结硅锗碳异质结双极晶体管(SiGeC HBT)新结构.详细分析了新结构中SiGeC基区和超结结构的引入对器件性能的影响,并对其电流输运机制进行研究.基于SiGeC/Si异质结技术,新结构器件的高频特性优良;同时超结结构的存在,在集电区内部水平方向和垂直方向都建立了电场,二维方向上的电场分布相互作用大大提高了新结构器件的耐压能力.结果表明:超结SiGeC HBT与普通结构SiGeC HBT相比,击穿电压提高了48.8%;更重要的是SiGeC HBT器件中超结结构的引入,不会改变器件高电流增益、高频率特性的优点;新结构器件与相同结构参数的Si双极晶体管相比,电流增益提高了10.7倍,截止频率和最高震荡频率也得到了大幅度改善,很好地实现了高电流增益、高频率特性和高击穿电压三者之间的折中.对超结区域的柱区层数和宽度进行优化设计,随着柱区层数的增多,击穿电压显著增大,电流增益有所提高,截止频率和最高震荡频率减低,但幅度很小.综合考虑认为超结区域采用pnpn四层结构是合理的.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

Omega shape channel LDMOS: A novel structure for high voltage applications

A new device structure for high breakdown voltage and low specific on resistance of the LDMOS device is proposed in this paper. The main idea in the proposed structure is using omega shape channel. The benefits of omega shape channel could be determined by extending depletion region in the drift region that causes low specific on resistance. Also, uniform horizontal electric field would be achieved that results in high breakdown voltage. The proposed structure is called Omega-shape Channel LDMOS (OCH-LDMOS). The simulation with two dimensional ATLAS simulator shows that the breakdown voltage increases to 712 V from 243 V of the conventional LDMOS at 12 µm drift length. Also, effective values of doping, length, and depth of Ω-shape channel are investigated.     

电极材料及偏压极性对氧化物介质击穿行为的影响及机制

忆阻器和能量存储电容器具有相同的三明治结构,然而两个器件需要的操作电压有明显差异,因此在同一个器件中,研究操作电压的影响因素并对操作电压进行调控,实现器件在不同领域的应用是十分必要的一个工作.本文利用反应磁控溅射技术在ITO导电玻璃、Pt/Si基底上生长了多晶ZrO_2和非晶TaO_x薄膜,选用不同金属材料Au, Ag和Al用作上电极构建了多种金属/氧化物介质/金属三明治结构的电容器,研究了器件在不同偏压极性下的击穿强度.结果发现:底电极是ITO的ZrO_2基电容器在负偏压下的击穿电场比Pt电极器件稍大.不管底电极是ITO还是Pt, Ag作为上电极时器件的击穿强度均存在明显的偏压极性依赖性,正偏压下的击穿电场减小了一个数量级;相反,在Al作为上电极的Al/TaO_x/Pt器件中,正向偏压比负向偏压下的击穿电场增加了近2倍.上述器件的不同击穿行为分别可以由氧化物电极和介质界面层间氧的迁移和重排、电化学活性金属电极的溶解迁移和还原以及化学活性金属电极与氧化物界面的氧化还原反应来解释.该实验结果对有不同操作电压要求的器件,如忆阻器和介质储能电容器等在器件设计和操作方面具有指导意义.