Oxygen Pressure Dependence of Properties of Epitaxial LaAlO3 Films Grown on Si （100）

Heteroepitaxial LaAlO3 films were grown on a SrTiO3/Si (100) substrate by laser molecular beam epitaxy under different oxygen pressures, and their properties such as crystallinity and electrical characteristics were experimentally investigated using the various measurement methods. The results show that most properties depend mainly on the deposition oxygen pressure. The crystallinity and the C-V and I-V characteristics can be greatly improved with the increasing oxygen deposition pressure. Moreover, after annealed at 1050~C in N2 ambient, the C-V and I-V characteristics of LAO films deposited at the lower oxygen pressure are also improved due to the decrease of oxygen vacancies in LAO films.     

Transient Hole Trapping in Individual GeSi Quantum Dot Grown on Si（001） Studied by Conductive Atomic Force Microscopy

Electrical properties of individual self-assembled GeSi quantum dots grown on Si substrates are investigated by using conductive atomic force microscopy at room temperature. By controlling the bias voltage sweep in a certain fast sweep rate range, a novel current peak is observed in the current-voltage characteristics of the quantum dots. The current peaks are detectable only during the backward voltage sweep immediately after a forward sweep. The current peak position and intensity are found to depend strongly on the voltage sweep conditions. This kind of current-voltage characteristic under fast sweep is very different from the ordinary steady state current behaviour of quantum dots measured previously. trapping in the potential well formed bottom Si substrate. The origin of this phenomenon by the quantum dot sandwiched can be attributed to the transient hole between the native oxide layer and the     

Ferroelectric effect and equivalent polarization charge model of PbZr_(0.2)Ti_(0.8)O_3 on AlGaN/GaN MIS-HEMT

PbZr_(0.2)Ti_(0.8)O_3(PZT) gate insulator with the thickness of 30 nm is grown by pulsed laser deposition(PLD) in AlGa N/Ga N metal–insulator–semiconductor high electron mobility transistors(MIS-HEMTs). The ferroelectric effect of PZT Al Ga N/Ga N MIS-HEMT is demonstrated. The polarization charge in PZT varies with different gate voltages. The equivalent polarization charge model(EPCM) is proposed for calculating the polarization charge and the concentration of two-dimensional electron gas(2 DEG). The threshold voltage(Vth) and output current density(IDS) can also be obtained by the EPCM. The theoretical values are in good agreement with the experimental results and the model can provide a guide for the design of the PZT MIS-HEMT. The polarization charges of PZT can be modulated by different gate-voltage stresses and the Vthhas a regulation range of 4.0 V. The polarization charge changes after the stress of gate voltage for several seconds. When the gate voltage is stable or changes at high frequency, the output characteristics and the current collapse of the device remain stable.     

CdS/Si nanofilm heterojunctions based on amorphous silicon films:Fabrication,structures,and electrical properties

Shortening the distance between the depletion region and the electrodes to reduce the trapped probability of carriers is a useful approach for improving the performance of heterojunction.The CdS/Si nanofilm heterojunctions are fabricated by using the radio frequency magnetron sputtering method to deposit the amorphous silicon nanofilms and Cd S nanofilms on the ITO glass in turn.The relation of current density to applied voltage(I-V)shows the obvious rectification effect.From the analysis of the double logarithm I-V curve it follows that below~2.73 V the electron behaviors obey the Ohmic mechanism and above~2.73 V the electron behaviors conform to the space charge limited current(SCLC)mechanism.In the SCLC region part of the traps between the Fermi level and conduction band are occupied,and with the increase of voltage most of the traps are occupied.It is believed that Cd S/Si nanofilm heterojunction is a potential candidate in the field of nano electronic and optoelectronic devices by optimizing its fabricating procedure.     

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors(JNTs) are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures(10 K–100 K) and variable drain bias voltages(10 mV–90 mV). Transfer characteristics exhibit current oscillation peaks below flat-band voltage(VFB) at temperatures up to 75 K,which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional(1D) channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.     

Ab initio investigation of boron nanodevices: conductances of the different geometric conformations

Conductances of different geometric conformations of boron ribbon devices are calculated by the ab initio method. The I-V characteristics of three devices are rather different due to the difference in structure. The current of the hexagonal boron device is the largest and increases nonlinearly. The current of the hybrid hexagon-triangle boron device displays a large low-bias current and saturates at a value of about 5.2 μA. The current of the flat triangular boron flake exhibits a voltage gap at low bias and rises sharply with increasing voltage. The flat triangular boron device can be either conducting or insulating, depending on the field.     

Structural and electrical characterization of annealed Si1-xCx/SiC thin film prepared by magnetron sputtering

Si-rich Sil-xCx/SiC multilayer thin films are prepared using magnetron sputtering, subsequently followed by thermal annealing in the range of 800-1200 ℃. The influences of annealing temperature （Ta） on the formation of Si and/or SiC nanocrystals （NCs） and on the electrical characteristics of the multilayer film are investigated by using a variety of analytical techniques, including X-ray diffraction （XRD）, Raman spectroscopy and Fourier transform infrared spectrometry （FT-IR）, current-voltage （I-V） technique, and capacitance-voltage （C-V） technique. XRD and Raman analyses indicate that Si NCs begin to form in samples for Ta _ 800 ~C. At annealing temperatures of 1000 ℃ or higher, the formation of Si NCs is accompanied by the formation of SiC NCs. With the increase in the annealing temperature, the shift of FT-IR Si-C bond absorption spectra toward a higher wave number along with the change of band shape can be explained by a Si-C transitional phase between the loss of substitutional carbon and the formation of SiC precipitates and a precursor for the growth of SiC crystalline. The C-V and I-V results indicate that the interface quality of Si1-xCx/SiC multilayer film is improved significantly and the leakage current is reduced rapidly for Ta ≥ 1000 ℃, which can be ascribed to the formation of Si and SiC NCs.     

Analysis on degradation mechanisms of normally-off p-GaN gate AlGaN/GaN high-electron mobility transistor

The degradation mechanisms of enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistor was analyzed extensively,by means of drain voltage stress and gate bias stress.The results indicate that:(ⅰ) High constant drain voltage stress has only a negligible impact on the device electrical parameters,with a slightly first increase and then decrease in output current;(ⅱ) A negative shift of threshold voltage and increased output current were observed in the device subjected to forward gate bias stress,which is mainly ascribed to the hole-trapping induced by high electric field across the p-GaN/AlGaN interface;(ⅲ) The analyzed device showed an excellent behavior at reverse gate bias stress,with almost unaltered threshold voltage,output current,and gate leakage current,exhibiting a large gate swing in the negative direction.The results are meaningful and valuable in directing the process optimization towards a high voltage and high reliable enhanced AlGaN/GaN high-electron mobility transistor.     

Effects of notch structures on DC and RF performances of AlGaN/GaN high electron mobility transistors

The effects of various notch structures on direct current(DC) and radio frequency(RF) performances of AlGaN/GaN high electron mobility transistors(HEMTs) are analyzed.The AlGaN/GaN HEMTs,each with a 0.8-μm gate length,50-μm gate width,and 3-μm source-drain distance in various notch structures at the AlGaN/GaN barrier layer,are manufactured to achieve the desired DC and RF characteristics.The maximum drain current(I_(ds,max)),pinch-off voltage(V_(th)),maximum transconductance(g_m),gate voltage swing(GVS),subthreshold current,gate leakage current,pulsed I-V characteristics,breakdown voltage,cut-off frequency(f_T),and maximum oscillation frequency(f_(max)) are investigated.The results show that the double-notch structure HEMT has a 30% improvement of gate voltage swing,a 42.2% improvement of breakdown voltage,and a 9% improvement of cut-off frequency compared with the conventional HEMT.The notch structure also has a good suppression of the current collapse.     

Comparative study of the electrical properties of Au/n-Si （MS） and Au/Si3N4/n-Si （MIS） Schottky diodes

In this paper,the electrical parameters of Au/n-Si(MS) and Au/Si3N4/n-Si(MIS) Schottky diodes are obtained from the forward bias current-voltage(I-V) and capacitance-voltage(C-V) measurements at room temperature.Experimental results show that the rectifying ratios of the MS and MIS diodes at±5 V are found to be 1.25 × 103 and 1.27 × 104,respectively.The main electrical parameters of the MS and MIS diodes,such as the zero-bias barrier height(ΦBo) and ideality factor(n),are calculated to be 0.51eV(I-V),0.53eV(C-V),and 4.43,and 0.65eV(I-V),0.70eV(C-V),and 3.44,respectively.In addition,the energy density distribution profile of the interface states(Nss) is obtained from the forward bias I-V,and the series resistance(Rs) values for the two diodes are calculated from Cheung's method and Ohm's law.     

Effect of Intra-Dot Coulomb Interaction on Andreev Reflection in Normal-Metal/Quantum-Dot/Superconductor System

We investigate the effect of intra-dot Coulomb interaction on the Andreev reflection in a normalmetal/quantum-dot/superconductor (N-QD-S) system with multiple levels in the quantum dot, in the regime where the intra-dot interacting constant is comparable to the energy gap of superconducting lead. By using nonequilibrium Green function method, the averaged occupation of electrons in the quantum dot and the Andreev reflection (AR) current are studied. Comparing to the case of non-interacting quantum dot, the system shows significant changes for the a two-step-like behavior; and the I-Vg shows two groups of peaks, separated by U and with equal heights, where Vg is the gate voltage and U denotes the intra-dot Coulomb interaction constant. (ii) For finite bias voltage, dips, superposed V ≥ U/2, extra AR current peaks occur between the two groups of the peaks. Besides, the properties of the heights of the AR current peaks are more complicated.``     

Different charging behaviors between electrons and holes in Si nanocrystals embedded in SiN_x matrix by the influence of near-interface oxide traps

Si-rich silicon nitride films are prepared by plasma-enhanced chemical vapor deposition method,followed by thermal annealing to form the Si nanocrystals(Si-NCs)embedded in Si Nx floating gate MOS structures.The capacitance–voltage(C–V),current–voltage(I–V),and admittance–voltage(G–V)measurements are used to investigate the charging characteristics.It is found that the maximum flat band voltage shift(△VFB)due to full charged holes(～6.2 V)is much larger than that due to full charged electrons(～1 V).The charging displacement current peaks of electrons and holes can be also observed by the I–V measurements,respectively.From the G–V measurements we find that the hole injection is influenced by the oxide hole traps which are located near the Si O2/Si-substrate interface.Combining the results of C–V and G–V measurements,we find that the hole charging of the Si-NCs occurs via a two-step tunneling mechanism.The evolution of G–V peak originated from oxide traps exhibits the process of hole injection into these defects and transferring to the Si-NCs.     

High-photosensitivity polymer thin-film transistors based on poly（3-hexylthiophene）

Polymer thin-film transistors(PTFTs) based on poly(3-hexylthiophene) are fabricated by the spin-coating process,and their photo-sensing characteristics are investigated under steady-state visible-light illumination.The photosensitivity of the device is strongly modulated by gate voltage under various illuminations.When the device is in the subthreshold operating mode,a significant increase in its drain current is observed with a maximum photosensitivity of 1.7×10 3 at an illumination intensity of 1200 lx,and even with a relatively high photosensitivity of 611 at a low illumination intensity of 100 lx.However,when the device is in the on-state operating mode,the photosensitivity is very low:only 1.88 at an illumination intensity of 1200 lx for a gate voltage of-20 V and a drain voltage of -20 V.The results indicate that the devices could be used as photo-detectors or sensors in the range of visible light.The modulation mechanism of the photosensitivity in the PTFT is discussed in detail.     

Electronic Properties of Nanocrystalline-Si Embedded in Asymmetric Ultrathin SiO2 by In-Situ Fabrication Technique

Structures of nanocrystalline-Si (nc-Si) sandwiched between two asymmetric ultrathin SiO2 layers were fabricated. The nc-Si (dot density of 10^11 cm^-2) was formed by decomposition of hydrogen-diluted silane and the ultrathin SiO2 layers (about 2 nm) were prepared by plasma oxidation at a lower temperature (250℃). The whole fabrication processes were completed in situ in a plasma-enhanced chemical vapour deposition system. By using the capacitance-voltage ( C-V) and conductance-voltage ( G-V) spectroscopy, we studied the electronic properties of the annealed samples. The experimental results show that there are distinct capacitance peaks and conductance plateau or peaks for annealed samples at room temperature, which can be explained by direct tunnelling of electrons into the nc-Si. At the same time, Coulomb blockade plays an important role in the electronic transport in the nc-Si. The effect of thermal annealing in N2 ambient on the electronic properties was studied and the results indicate that high temperature (1000℃) annealing can improve the size uniformity of the nc-Si prepared by decomposition of hydrogen-diluted silane.     

Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

The instability of p-channel low-temperature polycrystalline silicon thin film transistors(poly-Si TFTs) is investigated under negative gate bias stress(NBS) in this work. Firstly, a series of negative bias stress experiments is performed, the significant degradation behaviors in current–voltage characteristics are observed. As the stress voltage decreases from-25 V to-37 V, the threshold voltage and the sub-threshold swing each show a continuous shift, which is induced by gate oxide trapped charges or interface state. Furthermore, low frequency noise(LFN) values in poly-Si TFTs are measured before and after negative bias stress. The flat-band voltage spectral density is extracted, and the trap concentration located near the Si/SiO_2 interface is also calculated. Finally, the degradation mechanism is discussed based on the current–voltage and LFN results in poly-Si TFTs under NBS, finding out that Si–OH bonds may be broken and form Si*and negative charge OH-under negative bias stress, which is demonstrated by the proposed negative charge generation model.     

Investigation of a 4H-SiC metal-insulation-semiconductor structure with an Al2O3/SiO2 stacked dielectric

Atomic layer deposited(ALD) Al2O3 /dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8°off-axis 4H-SiC(0001) epitaxial wafers are investigated in this paper.The metal-insulation-semiconductor(MIS) capacitors,respectively with different gate dielectric stacks(Al2O3/SiO2,Al2O3,and SiO2) are fabricated and compared with each other.The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field(≥12 MV/cm) comparable to SiO2,and a relatively low gate leakage current of1×10-7A/cm2 at an electric field of4 MV/cm comparable to Al2O3.The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage,indicating a less effective charge and slow-trap density near the interface.     

The leakage current mechanisms in the Schottky diode with a thin Al layer insertion between Al0.245Ga0.755N/GaN heterostructure and Ni/Au Schottky contact

This paper investigates the behaviour of the reverse-bias leakage current of the Schottky diode with a thin Al inserting layer inserted between Al0.245Ga0.755 N/GaN heterostructure and Ni/Au Schottky contact in the temperature range of 25-350°C. It compares with the Schottky diode without Aluminium inserting layer. The experimental results show that in the Schottky diode with Al layer the minimum point of I-V curve drifts to the minus voltage, and with the increase of temperature increasing, the minimum point of I-V curve returns the 0 point. The temperature dependence of gate-leakage currents in the novelty diode and the traditional diode are studied. The results show that the Al inserting layer introduces interface states between metal and Al0.245Ga0.755N. Aluminium reacted with oxygen formed Al2O3 insulator layer which suppresses the trap tunnelling current and the trend of thermionic field emission current. The reliability of the diode at the high temperature is improved by inserting a thin Al layer.     

Studies of diamond-like carbon （DLC） films deposited on stainless steel substrate with Si/SiC intermediate layers

In this work, diamond-like carbon （DLC） films were deposited on stainless steel substrates with Si/SiC intermediate layers by combining plasma enhanced sputtering physical vapour deposition （PEUMS-PVD） and microwave electron cyclotron resonance plasma enhanced chemical vapour deposition （MW-ECRPECVD） techniques. The influence of substrate negative self-bias voltage and Si target power on the structure and nano-mechanical behaviour of the DLC films were investigated by Raman spectroscopy, nano-indentation, and the film structural morphology by atomic force microscopy （AFM）. With the increase of deposition bias voltage, the G band shifted to higher wave-number and the integrated intensity ratio ID/IG increased. We considered these as evidences for the development of graphitization in the films. As the substrate negative self-bias voltage increased, particle bombardment function was enhanced and the sp^3-bond carbon density reducing, resulted in the peak values of hardness （H） and elastic modulus （E）. Silicon addition promoted the formation of sp^3 bonding and reduced the hardness. The incorporated Si atoms substituted sp^2- bond carbon atoms in ring structures, which promoted the formation of sp^3-bond. The structural transition from C-C to C-Si bonds resulted in relaxation of the residual stress which led to the decrease of internal stress and hardness. The results of AFM indicated that the films was dense and homogeneous, the roughness of the films was decreased due to the increase of substrate negative self-bias voltage and the Si target power.     

Effect of F doping on capacitance-voltage characteristics of SiCOH low-k films metal-insulator-semiconductor

This paper investigates the capacitance-voltage(C-V) characteristics of F doping SiCOH low dielectric constant films metal-insulator-semiconductor structure.The F doping SiCOH films are deposited by decamethylcyclopentasiloxane(DMCPS) and trifluromethane(CHF3) electron cyclotron resonance plasmas.With the CHF3/DMCPS flow rate ratio from 0 to 0.52,the positive excursion of C-V curves and the increase of flat-band voltage VFB from 6.1 V to 32.2 V are obtained.The excursion of C-V curves and the shift of VFB are related to the change of defects density and type at the Si/SiCOH interface due to the decrease of Si and O concentrations,and the increase of F concentration.At the CHF3/DMCPS flow rate ratio is 0.12,the compensation of F-bonding dangling bond to Si dangling bond leads to a small VFB of 2.0 V.     

Improved breakdown voltage of AlGaN/GaN HEMTs grown on Si substrates using partially Mg-doped GaN buffer layer by MOCVD

AlGaN/GaN high electron mobility transistors(HEMTs) were grown on Si substrates by MOCVD.In the HEMT structure,a 1 μm GaN buffer layer was partially doped with Mg in an attempt to increase the resistivity and minimize the buffer leakage.The AlGaN/GaN HEMTs grown on undoped and partially Mg-doped GaN buffer layers were processed and the DC characteristics of the devices were characterized for comparing the effect of Mg doping.For the device with the partially Mg-doped GaN buffer layer,a lower drain leakage current density of 55.8 nA/mm,a lower gate leakage current density of 2.73 μA/mm,and a higher off-state breakdown voltage of 104 V were achieved with device dimensions Lg/Wg/Lgs/Lgd=1/10/1/1 μm,better than the device with the undoped GaN buffer layer,which has a higher drain leakage current density of 9.2 μA/mm,a higher gate leakage current density of 91.8 μA/mm,and a lower off-state breakdown voltage of 87 V with the same device dimensions.