Enhancement of fMAX of InP-based HEMTs by double-recessed offset gate process

A double-recessed offset gate process technology for InP-based high electron mobility transistors (HEMTs) has been developed in this paper. Single-recessed and double-recessed HEMTs with different gate offsets have been fabricated and characterized. Compared with single-recessed devices, the maximum drain-source current (I_D,max) and maximum extrinsic transconductance (g_m,max) of double-recessed devices decreased due to the increase in series resistances. However, in terms of RF performance, double-recessed HEMTs achieved higher maximum oscillation frequency (f_MAX) by reducing drain output conductance (g_ds) and drain to gate capacitance (C_gd). In addition, further improvement of f_MAX was observed by adjusting the gate offset of double-recessed devices. This can be explained by suppressing the ratio of C_gd to source to gate capacitance (C_gs) by extending drain-side recess length (L_rd). Compared with the single-recessed HEMTs, the f_MAX of double-recessed offset gate HEMTs was increased by about 20%.     

High-frequency enhancement-mode millimeterwave AlGaN/GaN HEMT with an fT/fmax over 100 GHz/200 GHz

Ultra-thin barrier (UTB) 4-nm-AlGaN/GaN normally-off high electron mobility transistors (HEMTs) having a high current gain cut-off frequency (f_T) are demonstrated by the stress-engineered compressive SiN trench technology. The compressive in-situ SiN guarantees the UTB-AlGaN/GaN heterostructure can operate a high electron density of 1.27×10¹³cm^-2, a high uniform sheet resistance of 312.8 Ω /□, but a negative threshold for the short-gate devices fabricated on it. With the lateral stress-engineering by full removing in-situ SiN in the 600-nm SiN trench, the short-gated (70 nm) devices obtain a threshold of 0.2 V, achieving the devices operating at enhancement-mode (E-mode). Meanwhile, the novel device also can operate a large current of 610 mA/mm and a high transconductance of 394 mS/mm for the E-mode devices. Most of all, a high f_T/f_max of 128 GHz/255 GHz is obtained, which is the highest value among the reported E-mode AlGaN/GaN HEMTs. Besides, being together with the 211 GHz/346 GHz of f_T/f_max for the D-mode HEMTs fabricated on the same materials, this design of E/D-mode with the realization of f_max over 200 GHz in this work is the first one that can be used in Q-band mixed-signal application with further optimization. And the minimized processing difference between the E- and D-mode designs the addition of the SiN trench, will promise an enormous competitive advantage in the fabricating costs.     

Improved device performance of recessed-gate AlGaN/GaN HEMTs by using in-situ N2O radical treatment

The N₂O radicals in-situ treatment on gate region has been employed to improve device performance of recessed-gate AlGaN/GaN high-electron-mobility transistors (HEMTs). The samples after gate recess etching were treated by N₂O radicals without physical bombardment. After in-situ treatment (IST) processing, the gate leakage currents decreased by more than one order of magnitude compared to the sample without IST. The fabricated HEMTs with the IST process show a low reverse gate current of 10^-9 A/mm, high on/off current ratio of 10⁸, and high f_T×L_g of 13.44 GHz· μm. A transmission electron microscope (TEM) imaging illustrates an oxide layer with a thickness of 1.8 nm exists at the AlGaN surface. X-ray photoelectron spectroscopy (XPS) measurement shows that the content of the Al-O and Ga-O bonds elevated after IST, indicating that the Al-N and Ga-N bonds on the AlGaN surface were broken and meanwhile the Al-O and Ga-O bonds formed. The oxide formed by a chemical reaction between radicals and the surface of the AlGaN barrier layer is responsible for improved device characteristics.     

High linearity AlGaN/GaN HEMT with double-Vth coupling for millimeter-wave applications

We demonstrated an AlGaN/GaN high electron mobility transistor(HEMT)namely double-Vthcoupling HEMT(DVC-HEMT)fabricated by connecting different threshold voltage(Vth)values including the slant recess element and planar element in parallel along the gate width with N;O plasma treatment on the gate region.The comparative studies of DVC-HEMT and Fin-like HEMT fabricated on the same wafer show significantly improved linearity of transconductance(Gm)and radio frequency(RF)output signal characteristics in DVC-HEMT.The fabricated device shows the transconductance plateau larger than 7 V,which yields a flattened fT/fmax-gate bias dependence.At the operating frequency of 30 GHz,the peak power-added efficiency(PAE)of 41%accompanied by the power density(Pout)of 5.3 W/mm.Furthermore,the proposed architecture also features an exceptional linearity performance with 1-d B compression point(P1 d B)of 28 d Bm,whereas that of the Fin-like HEMT is 25.2 d Bm.The device demonstrated in this article has great potential to be a new paradigm for millimeter-wave application where high linearity is essential.     

Ni/Au Schottky gate oxidation and BCB passivation for high-breakdown-voltage AlGaN/GaN HEMT

A new AlGaN/GaN high electron mobility transistor (HEMT) employing Ni/Au Schottky gate oxidation and benzocyclobutene (BCB) passivation is fabricated in order to increase a breakdown voltage and forward drain current. The Ni/Au Schottky gate metal with a thickness of 50/300 nm is oxidized under oxygen ambient at 500 C and the highly resistive NiO is formed at the gate edge. The leakage current of AlGaN/GaN HEMTs is decreased from 4.94 μA to 3.34 nA due to the formation of NiO. The BCB, which has a low dielectric constant, successfully passivates AlGaN/GaN HEMTs by suppressing electron injection into surface states. The BCB passivation layer has a low capacitance, so BCB passivation increases the switching speed of AlGaN/GaN HEMTs compared with silicon nitride passivation, which has a high dielectric constant. The forward drain current of a BCB-passivated device is 199 mA /mm, while that of an unpassivated device is 172 mA /mm due to the increase in two-dimensional electron gas (2DEG) charge.     

Effect of gate length on breakdown voltage in AlGaN/GaN high-electron-mobility transistor

The effects of gate length L_G on breakdown voltage VBRare investigated in AlGaN/GaN high-electron-mobility transistors(HEMTs) with L_G= 1 μm~20 μm. With the increase of L_G, VBRis first increased, and then saturated at LG= 3 μm. For the HEMT with L_G= 1 μm, breakdown voltage VBRis 117 V, and it can be enhanced to 148 V for the HEMT with L-_G= 3 μm. The gate length of 3 μm can alleviate the buffer-leakage-induced impact ionization compared with the gate length of 1 μm, and the suppression of the impact ionization is the reason for improving the breakdown voltage.A similar suppression of the impact ionization exists in the HEMTs with LG 3 μm. As a result, there is no obvious difference in breakdown voltage among the HEMTs with LG= 3 μm~20 μm, and their breakdown voltages are in a range of 140 V–156 V.     

AlGaN表面坑状缺陷及GaN缓冲层位错缺陷对AlGaN/GaN HEMT电流崩塌效应的影响

利用金属有机气相外延(MOVPE)技术生长了具有不同AlGaN表面坑状缺陷和GaN缓冲层位错缺陷密度的AlGaN/GaN 高电子迁移率晶体管(HEMT)样品,并对比研究了两种缺陷对器件栅、漏延迟电流崩塌效应的影响.栅延迟测试表明,AlGaN表面坑状缺陷会引起栅延迟电流崩塌效应和源漏电阻的增加,而且表面坑状缺陷越多,栅延迟电流崩塌程度和源漏电阻的增加越明显.漏延迟测试显示,AlGaN表面坑状缺陷对漏延迟电流崩塌影响不大,而GaN缓冲层位错缺陷主要影响漏延迟电流崩塌.研究结果表明,AlGaN表面坑状缺陷和Ga 关键词： AlGaN/GaN HEMT 电流崩塌 坑状缺陷 位错缺陷     

GaN HEMT栅边缘电容用于缺陷的研究

本文对GaN HEMT栅漏电容的频率色散特性进行分析,认为栅边缘电容的色散是导致栅漏电容频率色散特性不同于圆肖特基二极管电容的主要原因. 通过对不同栅偏置条件下缺陷附加电容与频率关系的拟合,发现小栅压下的缺陷附加电容仅满足单能级缺陷模型,而强反向栅压下的缺陷附加电容同时满足单能级和连续能级缺陷模型. 实验中栅边缘电容的频率色散现象在钝化工艺后出现,其反映的缺陷很可能是钝化工艺引入,且位于源漏间栅金属未覆盖区域的表面. 最后通过低频噪声技术进一步验证栅边缘电容提取缺陷参数的可行性. 低频噪声技术获得的单能级 关键词： HEMT 边缘电容 缺陷 低频噪声     

Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs

We fabricated a set of symmetric gate-recess devices with gate length of 70 nm.We kept the source-to-drain spacing(L_SD)unchanged,and obtained a group of devices with gate-recess length(L_recess)from 0.4μm to 0.8μm through process improvement.In order to suppress the influence of the kink effect,we have done SiN_X passivation treatment.The maximum saturation current density(ID_max)and maximum transconductance(g_m,max)increase as L_recess decreases to 0.4μm.At this time,the device shows ID_max=749.6 mA/mm at V_GS=0.2 V,V_DS=1.5 V,and g_m,max=1111 mS/mm at V_GS=?0.35 V,V_DS=1.5 V.Meanwhile,as L_recess increases,it causes parasitic capacitance C_gd and g_d to decrease,making f_max drastically increases.When L_recess=0.8μm,the device shows f_T=188 GHz and f_max=1112 GHz.     

Improvement of breakdown characteristics of an A1GaN/GaN HEMT with a U-type gate foot for millimeter-wave power application

<正>In this study,the physics-based device simulation tool Silvaco ATLAS is used to characterize the electrical properties of an AlGaN/GaN high electron mobility transistor(HEMT) with a U-type gate foot.The U-gate AlGaN/GaN HEMT mainly features a gradually changed sidewall angle,which effectively mitigates the electric field in the channel, thus obtaining enhanced off-state breakdown characteristics.At the same time,only a small additional gate capacitance and decreased gate resistance ensure excellent RF characteristics for the U-gate device.U-gate AlGaN/GaN HEMTs are feasible through adjusting the etching conditions of an inductively coupled plasma system,without introducing any extra process steps.The simulation results are confirmed by experimental measurements.These features indicate that U-gate AlGaN/GaN HEMTs might be promising candidates for use in miltimeter-wave power applications.     

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

A new ultra-low specific on-resistance(Ron,sp) vertical double diffusion metal–oxide–semiconductor field-effect transistor(VDMOS) with continuous electron accumulation(CEA) layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration(Nn). In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp.Especially, the two PN junctions within the trench gate support a high gate–drain voltage in the off-state and on-state, respectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS(CSJ-VDMOS)at the same high breakdown voltage(BV).     

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V_ds of 5.0 V is suppressed, whereas the drain leakage current at V_ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.     

Heterogeneous integration of InP HEMTs on quartz wafer using BCB bonding technology

Heterogeneous integrated InP high electron mobility transistors(HEMTs)on quartz wafers are fabricated successfully by using a reverse-grown InP epitaxial structure and benzocyclobutene(BCB)bonding technology.The channel of the new device is In_0.7Ga_0.3As,and the gate length is 100 nm.A maximum extrinsic transconductance gm,max of 855.5 mS/mm and a maximum drain current of 536.5 mA/mm are obtained.The current gain cutoff frequency is as high as 262 GHz and the maximum oscillation frequency reaches 288 GHz.In addition,a small signal equivalent circuit model of heterogeneous integration of InP HEMTs on quartz wafer is built to characterize device performance.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

场板结构AlGaN/GaN HEMT的电流崩塌机理

在不同的漏偏压下，研究了钝化和不同场板尺寸AlGaN/GaN HEMT对电流崩塌的抑制能力.实验结果表明，钝化器件对电流崩塌的抑制能力随着漏偏压的升高而显著下降；在高漏偏压下，场板的尺寸对器件抑制崩塌的能力有较大影响，而合适尺寸的场板结构在各个漏偏压下都能够很好的抑制电流崩塌.深入分析发现，场板结构不仅能够抑制虚栅的充电过程，而且提供了放电途径，有利于虚栅的放电，从而抑制电流崩塌.在此基础上，通过建立场板介质对虚栅放电的模型，解释了高漏偏压下场板的尺寸对器件抑制崩塌的能力有较大影响的原因.     

场板结构AlGaN/GaN HEMT的电流崩塌机理

在不同的漏偏压下,研究了钝化和不同场板尺寸AlGaN/GaN HEMT对电流崩塌的抑制能力.实验结果表明,钝化器件对电流崩塌的抑制能力随着漏偏压的升高而显著下降;在高漏偏压下,场板的尺寸对器件抑制崩塌的能力有较大影响,而合适尺寸的场板结构在各个漏偏压下都能够很好的抑制电流崩塌.深入分析发现,场板结构不仅能够抑制虚栅的充电过程,而且提供了放电途径,有利于虚栅的放电,从而抑制电流崩塌.在此基础上,通过建立场板介质对虚栅放电的模型,解释了高漏偏压下场板的尺寸对器件抑制崩塌的能力有较大影响的原因. 关键词： AlGaN/GaN HEMT 场板 电流崩塌     

Vertical polarization-induced doping InN/InGaN heterojunction tunnel FET with hetero T-shaped gate

A novel vertical InN/InGaN heterojunction tunnel FET with hetero T-shaped gate as well as polarization-doped source and drain region (InN-Hetero-TG-TFET) is proposed and investigated by Silvaco-Atlas simulations for the first time. Compared with the conventional physical doping TFET devices, the proposed device can realize the P-type source and N-type drain region by means of the polarization effect near the top InN/InGaN and bottom InGaN/InN heterojunctions respectively, which could provide an effective solution of random dopant fluctuation (RDF) and the related problems about the high thermal budget and expensive annealing techniques due to ion-implantation physical doping. Besides, due to the hetero T-shaped gate, the improvement of the on-state performance can be achieved in the proposed device. The simulations of the device proposed here in this work show I_ON of 4.45×10^-5 A/μm, I_ON/I_OFF ratio of 10¹³, and SS_avg of 7.5 mV/dec in InN-Hetero-TG-TFET, which are better than the counterparts of the device with a homo T-shaped gate (InN-Homo-TG-TFET) and our reported lateral polarization-induced InN-based TFET (PI-InN-TFET). These results can provide useful reference for further developing the TFETs without physical doping process in low power electronics applications.     

Fabrication and characterization of V-gate AlGaN/GaN high-electron-mobility transistors

V-gate GaN high-electron-mobility transistors (HEMTs) are fabricated and investigated systematically. A V-shaped recess geometry is obtained using an improved Si3N4 recess etching technology. Compared with standard HEMTs, the fabricated V-gate HEMTs exhibit a 17% higher peak extrinsic transconductance due to a narrowed gate foot. Moreover, both the gate leakage and current dispersion are dramatically suppressed simultaneously, although a slight degradation of frequency response is observed. Based on a two-dimensional electric field simulation using Silvaco "ATLAS" for both standard HEMTs and V-gate HEMTs, the relaxation in peak electric field at the gate edge is identified as the predominant factor leading to the superior performance of V-gate HEMTs.     

阶梯AlGaN外延新型Al0.25Ga0.75N/GaNHEMTs器件实验研究

本文报道了作者提出的阶梯AlGaN外延层新型AlGaN/GaN HEMTs结构的实验结果. 实验利用感应耦合等离子体刻蚀(ICP)刻蚀栅边缘的AlGaN外延层, 形成阶梯的AlGaN 外延层结构, 获得浓度分区的沟道2DEG, 使得阶梯AlGaN外延层边缘出现新的电场峰, 有效降低栅边缘的高峰电场, 从而优化了AlGaN/GaN HEMTs器件的表面电场分布. 实验获得了阈值电压-1.5 V的新型AlGaN/GaN HEMTs器件. 经过测试, 同样面积的器件击穿电压从传统结构的67 V提高到新结构的106 V, 提高了58%左右; 脉冲测试下电流崩塌量也比传统结构减少了30%左右, 电流崩塌效应得到了一定的缓解.     

基于脉冲方法的超短栅长GaN基高电子迁移率晶体管陷阱效应机理

陷阱效应导致的电流崩塌是制约GaN基微波功率电子器件性能提高的一个重要因素,研究深能级陷阱行为对材料生长和器件开发具有非常重要的意义.随着器件频率的提升,器件尺寸不断缩小,对小尺寸器件中深能级陷阱的表征变得越发困难.本文制备了超短栅长（L_g=80 nm）的AlGaN/GaN金属氧化物半导体高电子迁移率晶体管（MOSHEMT）,并基于脉冲I-V测试和二维数值瞬态仿真对器件的动态特性进行了深入研究,分析了深能级陷阱对AlGaN/GaN MOSHEMT器件动态特性的影响以及相关陷阱效应的内在物理机制.结果表明,AlGaN/GaN MOSHEMT器件的电流崩塌随着栅极静态偏置电压的增加呈非单调变化趋势,这是由栅漏电注入和热电子注入两种陷阱机制共同作用的结果.根据研究结果推断,可通过改善栅介质的质量以减小栅漏电或提高外延材料质量以减少缺陷密度等措施达到抑制陷阱效应的目的,从而进一步抑制电流崩塌.