Improvement of reverse blocking performance in vertical power MOSFETs with Schottky–drain-connected semisuperjunctions

To enhance the reverse blocking capability with low specific on-resistance,a novel vertical metal-oxidesemiconductor field-effect transistor(MOSFET) with a Schottky-drian(SD) and SD-connected semisuperjunctions(SDD-semi-SJ),named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional(2D) numerical simulations.The SD contacted with the n-pillar exhibits the Schottky-contact property,and that with the p-pillar the Ohmic-contact property.Based on these features,the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions(SJ) or semisuperjunctions(semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage(BV) and the specific on-resistance(R_(on)A).For a given pillar width and n-drift thickness,there exists a proper range of n-drift concentration(N),in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of R_(on)A-BV compared to the predication of SJ MOSFET in the forward applications.And what is much valuable,in this proper range of N,the desired BV and good trade-off could be achieved only by determining the pillar thickness,with the top assist layer thickness unchanged.Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of R_(on)A-BV improvement in SD-D-semi-SJ MOSFET.These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications.     

Low Specific On-Resistance SOI LDMOS with Non-Depleted Embedded P-Island and Dual Trench Gate

A new silicon-on-insulator(SOI) trench lateral double-diffused metal oxide semiconductor(LDMOS) with a reduced specific on-resistance R_(on),sp is presented. The structure features a non-depleted embedded p-type island(EP) and dual vertical trench gate(DG)(EP-DG SOI). First, the optimized doping concentration of drift region is increased due to the assisted depletion effect of EP. Secondly, the dual conduction channel is provided by the DG when the EP-DG SOI is in the on-state. The increased optimized doping concentration of the drift region and the dual conduction channel result in a dramatic reduction in R_(on),sp. The mechanism of the EP is analyzed,and the characteristics of R_(on),sp and breakdown voltage(BV) are discussed. Compared with conventional trench gate SOI LDMOS, the EP-DG SOI decreases R_(on),sp by 47.1% and increases BV from 196 V to 212 V at the same cell pitch by simulation.     

Effectiveness of inserting an In Ga N interlayer to improve the performances of In Ga N-based blue-violet laser diodes

Electron leakage still needs to be solved for In Ga N-based blue-violet laser diodes(LDs), despite the presence of the electron blocking layer(EBL). To reduce further electron leakage, a new structure of In Ga N-based LDs with an In Ga N interlayer between the EBL and p-type waveguide layer is designed. The optical and electrical characteristics of these LDs are simulated, and it is found that the adjusted energy band profile in the new structure can improve carrier injection and enhance the effective energy barrier against electron leakage when the In composition of the In Ga N interlayer is properly chosen. As a result, the device performances of the LDs are improved.     

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_on,sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R_on,sp compared to the SD device and HK device.     

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (R_on.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in R_on.sp by 45.7% simultaneously.     

A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

A uniform doping ultra-thin silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor(LDMOS)with low specific on-resistance(R_on,sp) and high breakdown voltage(BV) is proposed and its mechanism is investigated.The proposed LDMOS features an accumulation-mode extended gate(AG) and back-side etching(BE). The extended gate consists of a P– region and two diodes in series. In the on-state with VGD 0, an electron accumulation layer is formed along the drift region surface under the AG. It provides an ultra-low resistance current path along the whole drift region surface and thus the novel device obtains a low temperature distribution. The R_on,sp is nearly independent of the doping concentration of the drift region. In the off-state, the AG not only modulates the surface electric field distribution and improves the BV, but also brings in a charge compensation effect to further reduce the R_on,sp. Moreover, the BE avoids vertical premature breakdown to obtain high BV and allows a uniform doping in the drift region, which avoids the variable lateral doping(VLD) and the "hot-spot" caused by the VLD. Compared with the VLD SOI LDMOS, the proposed device simultaneously reduces the R_on,sp by 70.2% and increases the BV from 776 V to 818 V.     

Gallium- and iodine-co-doped titanium dioxide for photocatalytic degradation of 2-chlorophenol in aqueous solution: Role of gallium

Visible-light-driven TiO₂-based catalysts for the degradation of pollutants have become the focus of attention. In the present work, iodine-doped titania photocatalysts (I-TiO₂) were improved by doping with gallium (Ga,I-TiO₂) and the resulting physicochemical properties and photocatalytic activity were investigated. The structural properties of the catalysts were determined by X-ray diffraction, UV-vis diffuse reflectance spectroscopy, X-ray photoelectron spectroscopy, Brunauer-Emmett-Teller analysis and transmission electron microscopy. We found that Ga probably enters the TiO₂ framework for doping levels <0.5 mol%. A further increase in Ga content probably leads to dispersal of excess Ga on the TiO₂ surface. The photocatalytic activity of Ga,I-TiO₂ catalysts was evaluated using 2-chlorophenol (2-CP) as a model compound under visible and UV-vis light irradiation. The results indicate that 0.5 mol% Ga loading and calcination at 400 °C represent optimal conditions in the calcining temperature range 400-600 °C and with doping levels from 0.1% to 1 mol%. The effective enhancement of 2-CP degradation might be attributed to the formation of oxygen vacancies by Ga doping, which could decrease the recombination of electron-hole pairs.     

Advanced optical spectroscopy in nitrides and oxides: Some of the progress made during the past ten years

I review the recent progress made concerning the optical properties of (In,Al,Ga)N-based and (Zn,Mg)O-based epilayers and low dimensional systems like quantum wells, superlattices and microcavities.     

双空位掺杂氟化石墨烯的电子性质和磁性

基于密度泛函理论,计算了外来原子X(Al,P,Ga,As,Si)双空位替代掺杂氟化石墨烯的电子特性和磁性.通过对计算结果分析发现,与石墨烯的双空位掺杂类似,氟化石墨烯的双空位掺杂也是一种较为理想的掺杂方式.通过不同原子掺杂,氟化石墨烯的电子性质与磁性均发生很大变化:Al和Ga掺杂使氟化石墨烯由半导体变为金属,并且具有磁性;P和A8掺杂使氟化石墨烯变为自旋半导体;Si掺杂氟化石墨烯仍是半导体,只改变带隙且没有磁性.进一步讨论磁性产生机制获得了掺杂原子浓度与磁性的关系,并且发现不同掺杂情况的磁性是由不同原子的不同轨道电子引起的.双空位掺杂不仅丰富了氟化石墨烯的掺杂方式,其不同电磁特性也使此类掺杂结构在未来的电子器件中具有潜在应用.     

Influence of the grain boundary barrier height on the electrical properties of Gallium doped ZnO thin films

The pulsed laser deposition (PLD) technique is used to deposit Gallium doped zinc oxide (GZO) thin films on glass substrates at 250 with different Gallium (Ga) doping concentration of 0, 1.0, 3.0 and 5.0%. The influence of Ga doping concentration on structure, chemical atomic compositions, electrical and optical properties was investigated by XRD, XPS, Hall measurement and UV spectrophotometer, respectively. The relationship between electrical properties and Ga doping concentration was clarified by analyzing the chemical element compositions and the chemical states on the GZO films. It is found that the carrier concentrations and oxygen vacancies in the GZO films increase with increasing Ga doping concentration. The lowest resistivity (3.63 × 10⁻⁴ Ω cm) and barrier height of grain boundaries (14 mV) were obtained with 3% Ga doping. In particular, we suppose the band gap of 5% Ga doping sample larger than that of 3% Ga doping sample is due to the quantum size effect from the amorphous structure rather than Moss-Burstein shift.     

Cascaded deep ultraviolet light-emitting diode via tunnel junction

The Al Ga N-based deep ultraviolet(DUV) light-emitting diode(LED) is an alternative DUV light source to replace traditional mercury-based lamps. However, the state-of-the-art DUV LEDs currently exhibit poor wall-plug efficiency and low light output power, which seriously hinder their commercialization. In this work, we design and report a tunnel-junctioncascaded(TJC) DUV LED, which enables multiple radiative recombinations within the active regions. Therefore, the light output power of the TJC-DUV LEDs is more than doubled compared to the conventional DUV LED. Correspondingly, the wall-plug efficiency of the TJC-DUV LED is also significantly boosted by 25% at 60 m A.     

Ga掺杂对ZnO纳米结构可见光发射的抑制效应

采用碳热还原反应和原位掺杂的方法制备了不同Ga掺杂浓度的ZnO纳米结构. X射线衍射 显示掺杂纳米结构中为单一的氧化锌纤锌矿结构. 扫描电子显微镜 观测发现随掺杂浓度的增大, 纳米结构的形貌逐渐从纳米六棱柱变为纳米锥.光致发光 和X射线光电子能谱 测量分别发现随着掺杂浓度升高, 纳米结构的可见发光强度和其中空位 氧峰相对强度逐渐减小直至消失, 两者存在很强的相关性. 上述结果为ZnO可见光发射的氧空位机理提供了新的实验证据. 对Ga掺杂抑制纳米结构中氧空位的原因进行了分析.     

Effect of Barrier Temperature on Photoelectric Properties of Ga N-Based Yellow LEDs

The effect of growth temperature of barriers on photoelectric properties of Ga N-based yellow light emitting diodes(LEDs) is investigated. It is found that as the barrier temperature increases, the crystal quality of multiquantum wells(MQWs) and the quality of well/barrier interface are improved, and the quantum well is thermally annealed, so that the indium atoms in the quantum well migrate to the equilibrium position, reducing the phase separation of the quantum well and improving the crystal quality of quantum wells(QWs). However, the external quantum efficiency(EQE) of the samples begins to decrease when raising the barrier temperature even further.One explanation may be that the higher barrier temperature destroys the local state in the quantum well and reduces the well/barrier interface quality. Therefore, a suitable barrier temperature is proposed, contributing to the improvement of the luminous efficiency of the yellow LEDs.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.     

Experimental evaluation of interface states during time-dependent dielectric breakdown of GaN-based MIS-HEMTs with LPCVD-SiN_x gate dielectric

We experimentally evaluated the interface state density of Ga N MIS-HEMTs during time-dependent dielectric breakdown(TDDB). Under a high forward gate bias stress, newly increased traps generate both at the Si Nx/Al Ga N interface and the Si Nx bulk, resulting in the voltage shift and the increase of the voltage hysteresis. When prolonging the stress duration, the defects density generated in the Si Nx dielectric becomes dominating, which drastically increases the gate leakage current and causes the catastrophic failure. After recovery by UV light illumination, the negative shift in threshold voltage(compared with the fresh one) confirms the accumulation of positive charge at the Si Nx/Al Ga N interface and/or in Si Nx bulk, which is possibly ascribed to the broken bonds after long-term stress. These results experimentally confirm the role of defects in the TDDB of Ga N-based MIS-HEMTs.     

热退火处理对AuGeNi/n-AlGaInP欧姆接触性能的影响

本文在n-(Al0.27Ga0.73)0.5In0.5P表面通过电子束蒸发Ni/Au/Ge/Ni/Au叠层金属并优化退火工艺成功制备了具有较低接触电阻的欧姆接触,其比接触电阻率在445℃退火600 s时达到1.4×10–4 W·cm2.二次离子质谱仪测试表明,叠层金属Ni/Au/Ge/Ni/Au与n-AlGaInP界面发生固相反应,Ga,In原子由于热分解发生外扩散并在晶格中留下Ⅲ族空位.本文把欧姆接触形成的原因归结为Ge原子内扩散占据Ga空位和In空位作为施主提高N型掺杂浓度.优化退火工艺对低掺杂浓度n-(Al0.27Ga0.73)0.5In0.5P的欧姆接触性能有显著改善效果,但随着n-(Al0.27Ga0.73)0.5In0.5P掺杂浓度提高,比接触电阻率与退火工艺没有明显关系.本文为n面出光的AlGaInP薄膜发光二极管芯片的n电极制备提供了一种新的方法,有望大幅简化制备工艺,降低制造成本.     

镓铝双质掺杂提高晶闸管性能的机理研究

依据Ga,A1在Si和SiO2中的扩散行为和特性,采用SiO2/Si系统,利用磁控装置精确控制Ga掺杂量,实现镓铝双质掺杂在同一扩散炉中经一次高温连续完成.该项掺杂技术能实现Si中的高均匀掺杂,扩散参数具有良好的重复性和一致性,可获得较理想的杂质浓度分布.Ga,Al与Si的共价半径相接近,高温后又采取缓慢降温等措施,能明显减少晶格缺陷,提高少子寿命,降低压降.研究了受主双质掺杂与晶闸管参数之间的关系,并对镓铝双质掺杂提高晶闸管性能的机理进行了深入的分析与讨论.研究表明,镓铝双质受主掺杂有利于提高晶闸管的耐压水平和浪涌能力,能明显改善电流特性、触发特性和动态特性,优于其他受主掺杂技术.     

Magnetic Properties and Spin State Transition of Gallium Doped Perovskite Cobaltite Oxide

A series of Ga doping perovskite cobaltite La2/3Sr1/3 （Co1-y Gay）03 （y = 0, 0.1, 0.2, 0.3 and 0.4） are prepared by the standard solid-state reaction method. Their magnetic properties and Co ions spin state transitions are studied. Upon doping, no appreciable structure changes can be found. However, the corresponding Curie temperature sharply decreases and the magnetization is greatly reduced, indicating that Ga doping destroys the ferromagnetic interaction in the system. In addition, the high temperature magnetization data follow the Curie-Weiss law. At least one kind of Co ions （Co^3＋ or Co^4＋） favours the mixed spin state, and most Co ions are at the lower spin state （low and intermediate state）. With increasing Ga content, more Co ions transit to the higher spin state.     

Graded doping low internal loss 1060-nm InGaAs/AlGaAs quantum well semiconductor lasers

Internal loss is a key internal parameter for high power 1060-nm In Ga As/Al Ga As semiconductor laser.In this paper,we discuss the origin of internal loss of 1060-nm In Ga As/Ga As quantum well(QW) Al Ga As separate confinement heterostructure semiconductor laser,and the method to reduce internal loss.By light doping the n-cladding layer,and stepwise doping the p-cladding layer combined with the expanded waveguide layer,a broad area laser with internal loss of 1/cm is designed and fabricated.Ridge waveguide laser with an output power of 350 m W is obtained.The threshold current and slope efficiency near the threshold current are 20 m A and 0.8 W/A,respectively.     

Effect of synthesis conditions on microstructures and photoluminescence properties of Ga doped ZnO nanorod arrays

Ga doped ZnO nanorod arrays were prepared on silicon substrates in a mixture solution of zinc nitrate hexahydrate, methenamine, and gallium nitrate hydrate. Effect of synthesis conditions on crystal structures, morphologies, surface compositions, and optical properties was analyzed using X-ray diffraction (XRD), scanning electron microscopy (SEM), X-ray photoelectron spectroscopy (XPS), and photoluminescence techniques (PL). Experimental results reveal that Ga doping amount can reach 1.67 at% with the increase of gallium nitrate concentration. Ga doping greatly affects the morphologies of ZnO nanorod arrays. The photoluminescence spectra show a sharp UV emission and a broad visible emission. With Ga doping, UV emission has an apparent broadening effect and its peak shifts from 3.27 eV to 3.31 eV. The intensity ratio of UV emission to visible emission demonstrates that appropriate Ga doping amount is beneficial for the improvement of ZnO crystalline quality.