A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through(LPT) carrier stored trench bipolar transistor(CSTBT) with buried p-layer(BP) is proposed in this paper.Since the negative charges in the BP layer modulate the bulk electric field distribution,the electric field peaks both at the junction of the p base/n-type carrier stored(N-CS) layer and the corners of the trench gates are reduced,and new electric field peaks appear at the junction of the BP layer/N drift region.As a result,the overall electric field in the N drift region is enhanced and the proposed structure improves the breakdown voltage(BV) significantly compared with the LPT CSTBT.Furthermore,the proposed structure breaks the limitation of the doping concentration of the N-CS layer(NN CS) to the BV,and hence a higher NN CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop(Vce(sat)) can be obtained with almost constant BV.The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm-3,a thickness of LBP = 2.5 μm,and a width of WBP = 5 μm,the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V,with NN CS increasing from 5 × 1015 cm-3 to 2.5 × 1016 cm-3.However,with the same N-drift region thickness of 150 μm and NN CS,the BV of the CSTBT decreases from 1598 V to 247 V.Meanwhile,the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN CS increasing from 5 × 1015 cm-3 to 2.5 × 1016 cm-3.     

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n⁺-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n⁺-regions on the interface by the force with ionized donors in the undepleted n⁺-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E_I) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E_I of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.     

The influence of surface roughness in X-ray resonant magnetic reflectivity experiments

We present simulations of X-ray resonant magnetic reflectivity (XRMR) spectra of the surface magnetic dead layer in La_1−x Sr _x MnO₃ (LSMO) films that take in account the effect of different forms of roughness that can be encountered experimentally. The results demonstrate a method to distinguish between surface (morphological) roughness, and two generic kinds of magnetic roughness at the buried interface between the surface dead layer and the fully magnetic bulk part of the film. We show that the XRMR technique can distinguish between different types of magnetic roughness at the dead layer/bulk interface only if the sample surface is nearly atomically flat (the morphological roughness is one unit cell or less). Furthermore, to distinguish between the two types of magnetic roughness, the simulations show that fitting of XRMR spectra out to very high incidence angles must be performed. In the specific case of LSMO films with a dead layer with average thickness of 4 unit cells, this corresponds to an incidence angle > 50^∘.     

p型金属氧化物半导体场效应晶体管界面态的积累对单粒子电荷共享收集的影响

由于负偏置温度不稳定性和热载流子注入,p型金属氧化物半导体场效应晶体管(pMOSFET)将在工作中不断退化,而其SiO₂/Si界面处界面态的积累是导致其退化的主要原因之一. 采用三维器件数值模拟方法,基于130 nm体硅工艺,研究了界面态的积累对相邻pMOSFET之间单粒子电荷共享收集的影响. 研究发现,随着pMOSFET SiO₂/Si界面处界面态的积累,相邻pMOSFET漏端的单粒子电荷共享收集量均减少. 还研究了界面态的积累对相邻反相器中单粒子电荷共享收集 关键词： 负偏置温度不稳定性 电荷共享收集 双极放大效应 单粒子多瞬态     

Study on the deterioration process of bipolar coating using electrochemical impedance spectroscopy

A bipolar coating, which is composed of inner layer epoxy with nano SiO₂ modified by cetyltrimethylammonium bromide (CTAB) (containing positive fixed charge) and outer layer epoxy with nano SiO₂ modified by sodium dodecylbenzenesulfonate (SDBS) (containing negative charge), was prepared in this paper. Its deterioration process after exposure to 5% KCl solution was also studied by EIS measurement and SEM observation. The results indicate that the impedance module of the bipolar coating is about 1E+9 ohm after a longer time immersion period. The bipolar coating has a better anti-corrosion capacity than that of epoxy coating. The cation-selective outer layer in bipolar coating inhibits the aggressive anion, such as Cl⁻ ion, passing through the outer coating. Similarly, the anion-selective inner layer inhibits the metal cation passing through the inner coating. Thus the bipolar coating can protect the metal substrate from corrosion effectively. The p-n junction of bipolar coating, which has great charge storage ability, is the key factor in the anti-corrosion capacity of bipolar coating.     

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

New type Schottky diodes based on the heterostructure of transition metal oxides: p-La2/3Sr1/3VO3/n-TiO2

We make a new type of bipolar Schottky diodes using the p-type La_2/3Sr_1/3VO₃ (LSVO)/n-TiO₂ heterostructure. The p-type LSVO metal thin films are grown on various substrates using radio frequency magnetron co-sputtering deposition. We find that the LSVO film grown on anatase TiO₂ layer produce the lowest resistivity of 0.28 mΩ cm. We discover that the resistivity decreases with decreasing LSVO film thickness for LSVO/TiO₂/Si structures. Hall measurements are performed and the dielectric functions of LSVO films are measured. The effective mass of LSVO/TiO₂/Si is determined to be 2.54 ± 0.05 m₀. The current-voltage curves of the Schottky diodes of p-LSVO/n-TiO₂ is measured and is explained using band alignment diagram. We identify a new type of Schottky diode, where both electrons in n-TiO₂ and holes in p-LSVO can flow under bias.     

Fabrication and characterization of 4H—SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H-SiC bipolar junction transistor with a double base epilayer that is continuously grown.The measured dc common-emitter current gain is 16.8 at IC = 28.6 mA(J C = 183.4 A/cm2),and it increases with the collector current density increasing.The specific on-state resistance(Rsp-on) is32.3mΩ·cm 2 and the open-base breakdown voltage reaches 410 V.The emitter N-type specific contact resistance and N + emitter layer sheet resistance are 1.7×10-3 Ω·cm2 and 150 /,respectively.     

A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

Evolution of CoSi2 buried structures created by high temperature Co+ ion implantation into Si(1 0 0) during post-implantation annealing

The evolution of buried structures of cobalt disilicide, which are formed in a Si(1 0 0) matrix by 400 keV Co⁺ ion implantation at 875 K substrate temperature with subsequent rapid thermal annealing at 1275 K was studied by cross-sectional transmission electron microscopy (X-TEM). The analysis of identical samples with successive variations of the implanted doses and annealing times allows a detailed observation of the role of defects, created by the ion flux, on the process of ripening and growth of CoSi₂ precipitates. We found that transport of the implanted material along diffusive links leads to the formation of a secondary CoSi₂ distribution between the main layer and the surface. Post-implantation annealing results in the evolution of defects into dislocations, which affects the mobility and therefore the growth of CoSi₂ precipitates. Increasing the annealing time leads to the separate growth of precipitates in each layer. The result is not the formation of a single uniform buried layer because the distance between the individual layers is too large due to a screening effect, which operates during the ripening stage.     

Performance improvement in pentacene organic thin film transistors by inserting a C60 ultrathin layer

The contact effect on the performances of organic thin film transistors is studied here. A C₆₀ ultrathin layer is inserted between Al source--drain electrode and pentacene to reduce the contact resistance. By a 3 nm C₆₀ modification, the injection barrier is lowered and the contact resistance is reduced. Thus, the field-effect mobility increases from 0.12 to 0.52 cm²/(V·s). It means that inserting a C₆₀ ultra thin layer is a good method to improve the organic thin film transistor (OTFT) performance. The output curve is simulated by using a charge drift model. Considering the contact effect, the field effect mobility is improved to 1.15 cm²/(V·s). It indicates that further reducing the contact resistance of OTFTs should be carried out.     

中带电压法分离栅控横向pnp双极晶体管辐照感生缺

设计并制作了一种新型双极测试结构,即在常规横向pnp双极晶体管基区表面氧化层上淀积一栅电极,通过扫描栅极所加电压,获得漏极(集电极)电流随栅极电压的变化特性,利用中带电压法分离栅控横向pnp双极晶体管 在辐照过程中感生的氧化物陷阱电荷和界面陷阱电荷.本文对设计的晶体管测试结构和采用 的测试方法做了具体介绍.     

A novel structure of a high current gain 4H-SiC BJT with a buried layer in base

In this paper, a new structure of a 4H-SiC bipolar junction transistor (BJT) with a buried layer (BL) in the base is presented. The current gain shows an approximately 100% increase compared with that of the conventional structure. This is attributed to the creation of a built-in electric field for the minority carriers to transport in the base which is explained based on 2D device simulations. The optimized design of the buried layer region is also considered by numeric simulations.     

离子注入形成SOI结构的界面及埋层的俄歇能谱研究

本文中研究了O⁺(200keV,1.8×10¹⁸/cm²)和N⁺(190keV,1.8×10¹⁸/cm²)注入Si形成SOI(Silicon on Insulator)结构的界面及埋层的化学组成。俄歇能谱的测量和研究结果表明:注O⁺的SOI结构在经1300℃,5h退火后,其表层Si和氧化硅埋层的界面存在一个不饱和氧化硅状态,氧化硅埋层是由SiO₂相和这不饱和氧化硅态组成,而且氧化硅埋层和体硅界面不同于表层Si和氧化硅埋层界面;注N⁺的SOI结构在经1200℃,2h退火后,其氮化硅埋层中存在一个富N的疏松夹层,表层Si和氮化硅埋层界面与氮化硅埋层和体硅界面性质亦不同。这些结果与红外吸收和透射电子显微镜及离子背散射谱的分析结果相一致。还对两种SOI结构界面与埋层的不同特征的原因进行了分析讨论。 关键词：     

DCEMS of neon implantation in yttrium iron garnet

⁵⁷Fe-enriched, epitaxial Y₃Fe₅O₁₂ films have been implanted with 50 keV and 100 keV neon ions with a dose of 4·10¹⁴Ne⁺/cm². Depth-selective conversion electron Mössbauer spectroscopy has been performed at 300 K and 40 K. The results show that the 50 keV-implanted sample can be interpreted as an amorphous layer on top of an almost unperturbed YIG layer. In the 100 keV-implanted film a buried amorphous layer is observed.     

Substrate induced enhancement of atomic layer growth on Al(1 1 1): The effect of the mass anisotropy

The evolution of the thin-film morphology is studied by molecular dynamics simulations and we find a strong tendency of adatom island growth on the (1 1 1) surface of a thin Al overlayer placed on a heavy substrate (Pt(1 1 1)) when the system is subjected to low-energy Xe⁺ irradiation. The large adatom yield of 10²−10³ is found for 5-10 keV rare gas ion impacts. We also find that the mass effect due to the small atomic mass ratio (large mass anisotropy) in the bilayer has a direct effect on the atomic layer growth on the surface. A mass anisotropy induced scattering of the light overlayer atoms from the heavy substrate contributes to the enhancement of adatom production. It has been found that the volume increase (density decrease) of the amorphous intermixed phase keeps the adatoms on the surface. The competition between cratering and atomic layer growth can also be seen: three events out of 10 leads to cratering (erosion) morphology at 6 keV ion energy. The substrate induced enhancement of atomic layer growth might be a promising tool for making arrays of nanodots as nanotemplates for nanofabrication.     

Electrical properties and carrier transport mechanisms of nonvolatile memory devices based on randomly oriented ZnO nanowire networks

We report reproducible bipolar resistive memory devices based on Au/ZnO nanowire networks (ZnO NWNs)/ITO, which show a high R_on/R_off ratio (～10⁴) and narrow dispersion of set and reset threshold voltages. The dominant conduction mechanisms of low resistance state and high resistance state were verified by Ohmic behavior and space charge limited current, respectively. The switching mechanism is confirmed in terms of the formation and rupture of conductive filaments, with oxygen vacancies localized on the ZnO NWNs surface involved in. The Au/ZnO NWNs/ITO devices presented in our work show potential applications in the next generation nonvolatile memory field. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Molecular depth profiling of multi-layer systems with cluster ion sources

Cluster bombardment of molecular films has created new opportunities for SIMS research. To more quantitatively examine the interaction of cluster beams with organic materials, we have developed a reproducible platform consisting of a well-defined sugar film (trehalose) doped with peptides. Molecular depth profiles have been acquired with these systems using C₆₀⁺ bombardment. In this study, we utilize this platform to determine the feasibility of examining buried interfaces for multi-layer systems. Using C₆₀⁺ at 20 keV, several systems have been tested including Al/trehalose/Si, Al/trehalose/Al/Si, Ag/trehalose/Si and ice/trehalose/Si. The results show that there can be interactions between the layers during the bombardment process that prevent a simple interpretation of the depth profile. We find so far that the best results are obtained when the mass of the overlayer atoms is less than or nearly equal to the mass of the atoms in buried molecules. In general, these observations suggest that C₆₀⁺ bombardment can be successfully applied to interface characterization of multi-layer systems if the systems are carefully chosen.     

Novel partially depleted SOI MOSFET for suppression floating-body effect: An embedded JFET structure

Silicon-on-insulator (SOI) devices have an inherent floating body effect which may cause substantial influences in the performance of SOI devices and circuits. In this paper we propose a novel device structure to suppress the floating body effect by using an embedded junction field effect transistor (JFET). The key idea in this work is to provide a path for accumulated holes to flow out of the body to improving of electrical performance. We have introduced a p⁺-Si_1−xGe_x buried region under the n⁺-Si_1−xGe_x source and called the proposed structure as embedded JFET SOI MOSFET (EJFET–SOI). Using two-dimensional two-carrier simulation, the output and subthreshold characteristics of EJFET–SOI are compared with those of conventional SOI counterparts. The simulated results show the suppression of floating body effect in the EJFET–SOI structure as expected without consuming a significant amount of area.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.