Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

氮氟复合注入对注氧隔离SOI材料埋氧层内固定正电荷密度的影响

为了抑制埋层注氮导致的埋层内正电荷密度的上升, 本文采用氮氟复合注入方式, 向先行注氮的埋层进行了注氮之后的氟离子注入, 并经适当的退火, 对埋层进行改性. 利用高频电容-电压 (C-V) 表征技术, 对复合注入后的埋层进行了正电荷密度的表征. 结果表明, 在大多数情况下, 氮氟复合注入能够有效地降低注氮埋层内的正电荷密度, 且其降低的程度与注氮后的退火时间密切相关. 分析认为, 注氟导致注氮埋层内的正电荷密度降低的原因是在埋层中引入了与氟相关的电子陷阱. 另外, 实验还观察到, 在个别情况下, 氮氟复合注入引起了埋层内正电荷密度的进一步上升. 结合测量结果, 讨论分析了该现象产生的原因. 关键词： 绝缘体上硅(SOI) 材料 注氮 注氟 埋氧层正电荷密度     

离子注入形成SOI结构的界面及埋层的俄歇能谱研究

本文中研究了O⁺(200keV,1.8×10¹⁸/cm²)和N⁺(190keV,1.8×10¹⁸/cm²)注入Si形成SOI(Silicon on Insulator)结构的界面及埋层的化学组成。俄歇能谱的测量和研究结果表明:注O⁺的SOI结构在经1300℃,5h退火后,其表层Si和氧化硅埋层的界面存在一个不饱和氧化硅状态,氧化硅埋层是由SiO₂相和这不饱和氧化硅态组成,而且氧化硅埋层和体硅界面不同于表层Si和氧化硅埋层界面;注N⁺的SOI结构在经1200℃,2h退火后,其氮化硅埋层中存在一个富N的疏松夹层,表层Si和氮化硅埋层界面与氮化硅埋层和体硅界面性质亦不同。这些结果与红外吸收和透射电子显微镜及离子背散射谱的分析结果相一致。还对两种SOI结构界面与埋层的不同特征的原因进行了分析讨论。 关键词：     

SOIM新结构的制备及其性能的研究

制备在以SiO2为绝缘埋层的SOI材料上的电子器件存在着自加热问题.为减少自加热效应和满足一些特殊器件/电路的要求，利用多孔硅外延转移技术制备出以二氧化硅和氮化硅为多绝缘埋层的SOI新结构.高分辨率透射电镜和扩展电阻测试结果表明得到的SOIM新结构具有很好的结构和电学性能，退火后的氮化硅埋层为非晶结构.     

新型SOANN埋层SOI器件的自加热效应研究

本文提出了一个新型的SOI埋层结构SOANN (silicon on aluminum nitride with nothing),用AlN代替传统的SiO₂材料,并在SOI埋氧化层中引入空洞散热通道. 分析了新结构SOI器件的自加热效应.研究结果表明:用AlN做为SOI埋氧化层的材料, 降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道, 使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合, 有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

A novel lateral diffused metal oxide semiconductor (LDMOS) by attracting the electric field Lines

In this paper, a novel silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) transistor with high voltage and high frequency performance is presented. In this work we try to reduce the electric field crowding in the drift region. The proposed structure consists of a metal in the buried oxide and also connected to the source. The inserted metal attracts the electric field lines in the buried oxide. It causes 67% improvement in the breakdown voltage in comparison with a conventional SOI-LDMOS (C-LDMOS). Our simulations with two dimensional ATLAS simulator show that the gate-drain capacitance improves in the proposed structure. The unilateral power gain also enhances. So, the proposed structure is suitable for high voltage and high frequency applications.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

Double step buried oxide (DSBO) SOI-MOSFET: A proposed structure for improving self-heating effects

For the first time, a novel structure named as double step buried oxide silicon-on-insulator-MOSFET (DSBO-SOI) is proposed, which can combine the advantages of both SOI structure and bulk structure. Design consideration for a 30 nm channel length SOI-MOSFET employing double step buried oxide (DSBO) is presented. The electrical characteristics and temperature distribution are analyzed and compared with ultra-thin body silicon-on-insulator (UTB-SOI) MOSFET. The DSBO devices are shown to have better leakage and sub-threshold characteristics. Furthermore, the channel temperature is reduced during high-temperature operation and drain current increase suggesting that DSBO can mitigate the self-heating penalty effectively. Our results suggest that DSBO is an alternative to silicon dioxide as the buried dielectric in SOI, and expands the application of SOI to high temperature.     

基于智能剥离技术的SOI材料制备

优化了硅片低温直接键合与智能剥离技术的工艺流程，在550℃，2.1×10^-2 Pa条件下制备了SOI材料，其顶层单晶Si膜的表面粗糙度为8.5 nm，缺陷密度为90 cm^-2，键合强度达到153.7 kg/cm²，形成的SOI结构除了可以形成三维集成电路中有源层间良好的绝缘层，避免了高温过程对有源层器件结构、材料及性能的影响，还能为三维集成电路后续有源层的制造提供高质量的单晶硅材料. 关键词： 绝缘体上硅 智能剥离 低温直接键合     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal--Oxide--Semiconductor Field Effect Transistor

A novel fully depleted air A1N silicon-on-insulator （SOD metai-oxide-semiconductor field effect transistor （MOS- FET） is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75K higher than the atmosphere temperature, while the lattice temperature is just 4 K higher than the atmosphere temperature resulting in less severe self-heating effect in air A1N SOI MOSFETs and A1N SOI MOSFETs. The on-state current of air A1N SOI MOSFETs is similar to the A1N SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of A1N SOI is 6. 7 times of normal SOI MOSFETs, while the counterpart of air A1N SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air A1N SOl MOSFETs with different drain voltage is much less than that of A1N SOI devices, when the drain voltage is Mased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured.     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

Fabrication of freestanding nanoscale gratings on silicon-on-insulator wafer

We report a bottom-up process for the fabrication of freestanding nanoscale gratings on silicon-on-insulator (SOI) wafer. Freestanding membrane devices suffer deflection due to the residual stress of the buried oxide layer of SOI wafer. The deflection will affect the device shape and result in the fracture problem for devices fabricated on thin silicon membrane. The bottom-up process is developed to overcome the fabrication issue for thin silicon membrane gratings. The silicon handle layer is removed through back wafer etching of silicon, where the buried oxide layer acts as an etch stop layer. The grating structures are then defined on thin silicon device layer by electron beam lithography and generated by fast atom beam etching. The grating structures are finally released in vapor HF to form the freestanding nanoscale gratings. The freestanding linear/circular gratings, 1,500-nm period grating with the grating width of 200- and 850-nm period grating with the grating width of 100 nm, are successfully achieved on 260-nm silicon device layer.     

硅键合SOI平面光波导探索

本文分析了ＳＩＭＯＸ／ＳＯＩ和ＤＷＢ／ＳＯＩ结构的性能特点。尝试用ＤＷＢ／ＳＯＩ材料制备不同波导层厚度的平面光波导样品，并测试了１．１５μｍ和１．５２３μｍ激光的ＴＥ和ＴＭ模的传输损耗。１．５２３μｍ光的ＴＥ模的最小传输损耗已达０．２７ｄＢ／ｃｍ。说明ＤＷＢ／ＳＯＩ材料是一种有潜力的光波导材料。     

A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance.     

Improvement of total-dose irradiation hardness of silicon-on-insulator materials by modifying the buried oxide layer with ion implantation

The hardening of the buried oxide (BOX) layer of separation by implanted oxygen (SIMOX) silicon-on-insulator (SOI) wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad(SiO₂. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.