双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

In this paper for the first time, a partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) is proposed with a novel trench which improves breakdown voltage. The introduced trench in the partial buried oxide enhances peak of the electric field and is positioned in the drain side of the drift region to maximize breakdown voltage. We demonstrate that the electric field is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the trench-partial-silicon-on-insulator (T-PSOI) structure. Hence, a more uniform electric field is obtained. Two dimensional (2D) simulations show that the breakdown voltage of T-PSOI is nearly 64% higher in comparison with partial silicon on insulator (PSOI) structure and alleviate self heating effect approximately 9% and 15% in comparison with its conventional PSOI (C-PSOI) and conventional SOI (C-SOI) counterparts respectively. In addition the current of the T-PSOI, C-PSOI, conventional SOI (C-SOI), and fully depleted conventional SOI (FC-SOI) structures are 90, 82, 74, and 44 μA, respectively for a drain–source voltage V_DS = 30 V and gate–source voltage V_GS = 10 V.     

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

New CMOS compatible super junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET (LDMOST) structure is designed with n-type charge compensation layer embedded in the p$^{ - }$-substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p$^{ - }$-substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field (REBULF) is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain. The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using a SiGe zone in drift region

High breakdown voltage and reduced on-resistance are desired characteristics in power MOSFETs. In order to obtain an excellent performance of Trench Gate Power MOSFET, we have proposed a new structure in which a SiGe zone is incorporated in the drift region to reduce on-resistance. Also, the buried oxide is considered in the drift region that surrounds the SiGe zone to increase breakdown voltage. The proposed structure is called a SiGe Zone Trench Gate MOSFET (SZ-TG). Our simulation with two dimensional simulator shows that by reducing an electric field and controlling the effects of parasitic BJT transistor in the SZ-TG structure, we can expand power applications of trench gate power structures.     

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm~2,因此获得了高达1966 MW·cm~(-2)的品质因数(FOM=BV~2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.     

阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

Analysis of the modulation mechanisms of the electric field and breakdown performance in AlGaN/GaN HEMT with a T-shaped field-plate

A novel Al Ga N/Ga N high electron mobility transistor(HEMT) with a source-connected T-shaped field-plate(ST-FP HEMT) is proposed for the first time in this paper. The source-connected T-shaped field-plate(ST-FP) is composed of a source-connected field-plate(S-FP) and a trench metal. The physical intrinsic mechanisms of the ST-FP to improve the breakdown voltage and the FP efficiency and to modulate the distributions of channel electric field and potential are studied in detail by means of two-dimensional numerical simulations with Silvaco-ATLAS. A comparison to the HEMT and the HEMT with an S-FP(S-FP HEMT) shows that the ST-FP HEMT could achieve a broader and more uniform channel electric field distribution with the help of a trench metal, which could increase the breakdown voltage and the FP efficiency remarkably. In addition, the relationship between the structure of the ST-FP, the channel electric field, the breakdown voltage as well as the FP efficiency in ST-FP HEMT is analyzed. These results could open up a new effective method to fabricate high voltage power devices for the power electronic applications.     

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n⁺-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n⁺-regions on the interface by the force with ionized donors in the undepleted n⁺-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E_I) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E_I of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.     

新型SOANN埋层SOI器件的自加热效应研究

本文提出了一个新型的SOI埋层结构SOANN (silicon on aluminum nitride with nothing),用AlN代替传统的SiO₂材料,并在SOI埋氧化层中引入空洞散热通道. 分析了新结构SOI器件的自加热效应.研究结果表明:用AlN做为SOI埋氧化层的材料, 降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道, 使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合, 有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.     

Novel fast-switching LIGBT with P-buried layer and partial SOI

A novel silicon-on-insulator lateral insulated gate bipolar transistor(SOI LIGBT)is proposed in this paper.The proposed device has a P-type buried layer and a partial-SOI layer,which is called the BPSOI-LIGBT.Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer,the proposed structure generates two new peaks in the surface electric field distribution,which can achieve a smaller device size with a higher breakdown voltage.The smaller size of the device is beneficial to the fast switching.The simulation shows that under the same size,the breakdown voltage of the BPSOI LIGBT is 26%higher than that of the conventional partial-SOI LIGBT(PSOI LIGBT),and 84%higher than the traditional SOI LIGBT.When the forward voltage drop is 2.05 V,the turn-off time of the BPSOI LIGBT is 71%shorter than that of the traditional SOI LIGBT.Therefore,the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT.In addition,the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

具有N型缓冲层REBULF Super Junction LDMOS

针对功率集成电路对低损耗LDMOS (lateral double-diffused MOSFET)类器件的要求,在N型缓冲层super junction LDMOS (buffered SJ-LDMOS)结构基础上, 提出了一种具有N型缓冲层的REBULF (reduced BULk field) super junction LDMOS结构. 这种结构不但消除了N沟道SJ-LDMOS由于P型衬底带来的衬底辅助耗尽效应问题, 使super junction的N区和P区电荷完全补偿, 而且同时利用REBULF的部分N型缓冲层电场调制效应, 在表面电场分布中引入新的电场峰而使横向表面电场分布均匀, 提高了器件的击穿电压. 通过优化部分N型埋层的位置和参数, 利用仿真软件ISE分析表明, 新型REBULF SJ-LDMOS 的击穿电压较一般LDMOS提高了49%左右, 较文献提出的buffered SJ-LDMOS结构提高了30%左右. 关键词： lateral double-diffused MOSFET super junction 击穿电压 表面电场     

Improvement on the breakdown voltage for silicon-on-insulator devices based on epitaxy-separation by implantation oxygen by a partial buried n+-layer

A novel silicon-on-insulator (SOI) high-voltage device based on epitaxy-separation by implantation oxygen (SIMOX) with a partial buried n⁺-layer silicon-on-insulator (PBN SOI) is proposed in this paper. Based on the proposed expressions of the vertical interface electric field, the high concentration interface charges which are accumulated on the interface between top silicon layer and buried oxide layer (BOX) effectively enhance the electric field of the BOX (E_I), resulting in a high breakdown voltage (BV) for the device. For the same thicknesses of top silicon layer (10 μm) and BOX (0.375 upmum), the E_I and BV of PBN SOI are improved by 186.5% and 45.4% in comparison with those of the conventional SOI, respectively.     

Electric field modulation technique for high-voltage AlGaN/GaN Schottky barrier diodes

A novel structure of AlGaN/GaN Schottky barrier diode(SBD) featuring electric field optimization techniques of anode-connected-field-plate(AFP) and magnesium-doped p-type buried layer under the two-dimensional electron gas(2DEG) channel is proposed.In comparison with conventional AlGaN/GaN SBDs,the magnesium-doped p-type buried layer in the proposed structure can provide holes that can help to deplete the surface 2DEG.As a result,surface field strength around the electrode edges is significantly suppressed and the electric field along the channel is distributed more evenly.Through 2D numerical analysis,the AFP parameters(field plate length,L AFP,and field plate height,T AFP) and p-type buried layer parameters(p-type layer concentration,N P,and p-type layer thickness,T P) are optimized to achieve a three-equal-peak surface channel field distribution under exact charge balance conditions.A novel structure with a total drift region length of 10.5 μm and a magnesium-doped p-type concentration of 1 × 1017cm-3achieves a high breakdown voltage(V B) of 1.8 kV,showing 5 times improvement compared with the conventional SBD with the same device dimension.     

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator(SOI) high breakdown voltage(BV) power device with interlaced dielectric trenches(IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges(holes) at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.