硅基聚合物AWG波分复用器研究

报道利用甲基丙稀酸甲酯-甲基丙稀酸缩水甘油酯共聚物研制AWG波分复用器，对其原理、设计及制作工艺进行了研究。设计出AWG版图，利用铝掩模技术及反应离子刻蚀工艺完成了聚合物AWG制作。实验结果证明，制备的波导实现了单模传输。     

聚合物阵列波导光栅复用器关键技术的研究

介绍了阵列波导光栅(AWG)复用器的工作原理;运用光栅衍射理论和马卡提里近似法,对中心波长为1.55 μm,波长间隔为1.6 nm的聚合物AWG进行参量设计,通过数值模拟验证了设计的正确性.用甲基丙烯酸甲酯类聚合物对AWG的制备工艺进行了研究,用铝作掩模制作了聚合物光波导,测试结果表明在1.55 μm处波导实现单模传输.     

人工裁剪制备石墨纳米结构

采用不同的方法裁剪高定向热解石墨（HOPG），制备纳米尺寸的石墨条.首先,发现用聚焦离子束（镓离子）刻蚀高定向热解石墨，可以得到边缘整齐程度在几十纳米的石墨条,另外,用 电子束曝光和反应离子刻蚀的工艺，可以得到最小尺寸为50 nm的纳米石墨图型 (nano-size d graphite pattern,纳米尺寸的多层石墨结构).采用了三种不同的方案制备反应等离子刻 蚀过程中需要的掩膜，分别是PECVD生长的SiO₂掩膜，磁控溅射的方法生长的Si O₂掩膜和PMMA光刻胶掩膜，并将三种方案的刻蚀结果做了对比. 关键词： 高定向热解石墨 聚焦离子束刻蚀 电子束曝光 反应离子刻蚀     

亚微米尺寸元件的离子束刻蚀制作

采用软光刻技术中的微接触印刷(μCP)技术、表面诱导的水蒸气冷凝、表面诱导的去湿行为,在金基底上制作出了亚微米的环状周期结构聚合物掩膜.通过对离子束刻蚀过程中各个参量对刻蚀元件的表面光洁度、轮廓保真度和线宽分辨的影响分析,结合掩膜的实际情况选择出了合适的离子束入射角、离子能量、束流密度和刻蚀时间等参量.依照这些参量刻蚀出了高质量的亚微米尺寸环状周期结构元件.通过对刻蚀出的元件的检测发现,刻出的元件表面光洁度、轮廓保真度和侧壁陡峭度都非常好.     

减少聚合物阵列波导光栅损耗的蒸气回溶技术

阵列波导光栅(AWG)器件是波分复用(WDM)系统的一种关键器件,其中,聚合物阵列波导光栅由于其制备工艺、器件集成等方面的优势而受到人们的日益关注。侧壁散射损耗是聚合物阵列波导光栅损耗的一个主要因素,减少阵列波导光栅波导的侧壁损耗对制备低损耗阵列波导光栅具有重要意义。一种蒸气回溶技术被用来有效地减少硅基聚合物阵列波导光栅的散射损耗,该技术的机理是饱和溶剂分子融入并软化波导侧壁,增加其流动性,从而降低波导侧壁粗糙度。用扫描电镜方法验证了用该技术能获得更光滑的波导侧壁。对直波导和阵列波导光栅样品进行回溶处理,测试后得到直波导的侧壁散射损耗减少2.1 dB/cm,阵列波导光栅中心信道和周边信道的插入损耗分别减少5.5 dB和6.7 dB,串扰减少2.5 dB。     

掺杂LaF3∶Er,Yb纳米颗粒的有机无机复合型平面光波导放大器的制备及增益测试

采用油酸修饰的铒镱共掺氟化镧纳米颗粒掺杂的有机-无机杂化材料做为光波导放大器的有源层,同时采用光学性质良好的甲基丙烯酸甲酯-甲基丙烯酸环氧丙酯共聚物制作光波导的上下包层,首先说明了芯层材料不能刻蚀制备传统矩形波导的原因,其次设计了一种倒脊结构的平面光波导放大器,并采用蒸镀铝掩膜、紫外光刻和反应离子刻蚀等工艺,制备出放大器的样品,同时对样品端面进行了化学机械抛光处理,在信号光（1 550 nm）功率为1 mW的条件下,在1.9 cm长度的波导上获得了3.2 dB的相对增益.     

掺杂LaF3:Er,Yb纳米颗粒的有机无机复合型平面光波导放大器的制备及增益测试

采用油酸修饰的铒镱共掺氟化镧纳米颗粒掺杂的有机-无机杂化材料做为光波导放大器的有源层,同时采用光学性质良好的甲基丙烯酸甲酯-甲基丙烯酸环氧丙酯共聚物制作光波导的上下包层,首先说明了芯层材料不能刻蚀制备传统矩形波导的原因,其次设计了一种倒眷结构的平面光波导放大器,并采用蒸镀铝掩膜、紫外光刻和反应离子刻蚀等工艺,制备出放大...     

高品质因子聚合物波导微环谐振腔滤波器

基于紫外固化胶和聚砜聚合物材料体系,采用脊形单模波导结构,理论设计并优化了聚合物波导环形谐振腔滤波器的波导截面参数、弯曲半径和耦合区波导间距等结构参数,分析了其滤波响应特性.并在此基础上,结合光刻、反应离子刻蚀等传统的微加工工艺制备了聚合物环形谐振腔滤波器,并进行了光谱测试,器件测试结果与设计基本符合.结果表明,该聚合物微环谐振腔滤波器在通信波段1550 nm附近的自由光谱范围为0.21 nm,3 dB带宽为0.04 nm,插入损耗为26 dB,消光比达到了11 dB,品质因子达到了3.87×104.该聚合物微环谐振腔滤波器可以用于光通信及光传感集成芯片.     

一种简单高效的制备硅纳米孔阵结构的方法

本文介绍了一种简单高效的制备硅纳米孔阵结构的方法. 利用激光干涉光刻技术, 结合干法和湿法刻蚀工艺, 直接将光刻胶点阵刻蚀为硅纳米孔阵结构, 省去了图形反转工艺中的金属蒸镀和光刻胶剥离等必要步骤, 在2英寸的硅 (001) 衬底上制备了高度有序的二维纳米孔阵结构. 利用干法刻蚀产生的氟碳有机聚合物作为湿法刻蚀的掩膜, 以及在干法刻蚀时对样品进行轻微的过刻蚀, 使SiO₂点阵图形下形成一层很薄的硅台面, 是本方法的两个关键工艺步骤. 扫描电子显微镜图片结果表明制备的孔阵图形大小均匀, 尺寸可控, 孔阵周期为450 nm, 方孔大小为200–280 nm. 关键词： 激光干涉光刻 纳米阵列 刻蚀 氟碳有机聚合物     

纳米金属掩膜和离子辐照技术制备高温超导约瑟夫森结

研究了一种利用纳米金属掩膜和离子辐照技术在高温超导YBCO薄膜上制备Josephson结的方法.首先用在YBCO薄膜甩上一层800nm左右的光刻胶(PMMA),继而在光刻胶上用直流磁控溅射的方法镀上一层大约300nm左右的Cr膜,利用紫外曝光和离子刻蚀的方法在YBCO薄膜上形成覆盖有Cr膜的微桥,然后,利用聚焦离子束系统(FIB)在微桥上刻出一个50nm左右的狭缝,最后利用120keV的H2 对狭缝内的材料进行辐照,从而使狭缝部分的材料超导电性减弱,形成类似SNS型的Josephson结.     

Atomic force microscopy investigation of surface roughness generated between SiO2 micro-pits in CHF3/Ar plasma

The present paper investigates the surface roughness generated by reactive ion etching (RIE) on the location between silicon dioxide (SiO₂) micro-pits structures. The micro-pit pattern on polymethyl methacrylate (PMMA) mask was created by an electron beam lithography tool. By using PMMA as a polymer resist mask layer for pattern transfer in RIE process, the carbon (C) content in etching process is increased, which leads to decrease of F/C ratio and causes domination of polymerization reactions. This leads to high surface roughness via self-organized nanostructure features generated on SiO₂ surface which was analyzed using atomic force microscopy (AFM) technique. The etching chemistry of CHF₃ plasma on PMMA masking layer and SiO₂ is analyzed to explain the polymerization. The surface root-mean-square (RMS) roughness below 1 nm was achieved by decreasing the RF power to 150 W and process pressure lower than 10 mTorr.     

Polymeric 32-channel arrayed waveguide grating multiplexer using fluorinated poly (ether ether ketone)

In wavelength division multiplexing (WDM) systems, an arrayed waveguide grating (AWG) multiplexer is a key component. A polymeric AWG multiplexer has recently attracted much attention due to its low cost processing and a potential of integration with other devices. Fluorinated poly (ether ether ketone)(FPEEK) is excellent material for fabrication of optical waveguides due to its low absorption loss at 1.55-μm wavelength and high thermal stability. A 32-channel AWG multiplexer has been designed based on the grating diffraction theory and fabricated using newly synthesized FPEEK. During the fabrication process of the Polymer/Si AWG device, spin coating, vaporizing, photolithographic patterning and reactive ion etching (RIE) are used. The AWG multiplexer measurement system is based on a tunable semiconductor laser, infrared camera and a Peltier-type heater. The device exhibits a wavelength channel spacing of 0.8nm and a center wavelength of 1548 nm in the room temperature.     

Reactive ion etching of FePt using inductively coupled plasma

We propose a reactive ion etching (RIE) process of an L1₀-FePt film which is expected as one of the promising materials for the perpendicular magnetic recording media. The etching was carried out using an inductively coupled plasma (ICP) RIE system and an etching gas combination of CH₄/O₂/NH₃ was employed. The L1₀-FePt films were deposited on (1 0 0)-oriented MgO substrates using a magnetron sputtering system. The etching masks of Ti were patterned on the FePt films lithographically. The etch rates of ∼16 and ∼0 nm/min were obtained for the FePt film and the Ti mask, respectively. The atomic force microscopy (AFM) analyses provided the average roughness (R_a) value of 0.95 nm for the etched FePt surface, that is, a very flat etched surface was obtained. Those results show that the highly selective RIE process of L1₀-FePt was successfully realized in the present study.     

Modern Applications of Plasma Etching and Patterning in Silicon Process Technology

Besides plasma etching of through-wafer interconnects in wafer stacks for vertical integration of chips, fabrication of platinum (Pt) electrodes with non-tapered sidewalls for the storage node in modern memories (DRAMs and FeRAMs) is one of the most challenging tasks of plasma process technology today. This paper describes the achievement of vertical integration of chips by plasma etching of high aspect ratio interchip vias. The etching processes for dielectrics, single crystal silicon, and the organic glue layer were all optimized for minimum reactive ion etching (RIE) lag i.e. for minimum decrease of etch rate with increasing etch depth. Furthermore the fabrication of perfect Pt electrodes for modern DRAMs and FeRAMs is reported. Vertical Pt profiles were achieved by plasma processing with resist mask. In this novel approach, the build-up of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the pre-etch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by chemical mechanical polishing.     

Fabrication of Nanoimprint Stamp Using Interference Lithography

Interference lithography is used to fabricate a nanoimprint stamp, which is a key step for nanoimprint lithography. A layer of chromium in thickness of about 20 nm is deposited on the newly cleaned fused silica substrate by thermal evaporation, and a layer of positive resist in thickness of 150nm is spun on the chromium layer. Some patterns, including lines, holes and pillars, are observed on the photoresist film by exposing the resist to interference patterns and they are then transferred to the chromium layer by wet etching. Fused silica stamps are fabricated by reactive ion etching with CHF3/O2 as etchants using the chromium layer as etch mask. An atomic force microscope is used to analyse the pattern transfer in each step. The results show that regular hole patterns of fused silica, with average full width 143nm at half maximum （FWHM）, average hole depth of 76nm and spacing of 450nm, have been fabricated. The exposure method is fast, inexpensive and applicable for fabrication of nanoimprint stamps with large areas.     

基于直接胶体晶体刻蚀技术的高度有序纳米硅阵列的尺寸及形貌控制

以自组装单层胶体小球阵列为掩模，采用直接胶体晶体刻蚀技术在硅表面制备二维有序尺寸可控的纳米结构.在样品制备过程中，首先通过自组装法在硅表面制备了直径200nm的单层聚苯乙烯(PS)胶体小球的二维有序阵列；然后对样品直接进行反应离子刻蚀(RIE)，以氧气为气源，利用氧等离子体对聚苯乙烯小球和对硅的选择性刻蚀作用，通过改变刻蚀时间，制备出不同尺寸的PS胶体小球的有序单层阵列；接着以此二维PS胶体单层膜为掩模，以四氟化碳为气源对样品进行刻蚀；最后去除胶体球后得到二维有序的硅柱阵列.SEM和AFM的测量结果表明：改变氧等离子体对胶体球的刻蚀时间和四氟化碳对硅的刻蚀时间，可以控制硅柱的尺寸以及形貌，而硅柱阵列的周期取决于原始胶体球的直径. 关键词： 胶体晶体刻蚀 纳米硅柱阵列     

Large-area micro/nanostructures fabrication in quartz by laser interference lithography and dry etching

Laser interference lithography (LIL) has the capability to fabricate large-area microstructures on the photoresist with only a couple of minutes’ exposure and development. In this study, LIL was adopted to fabricate micro/nanostructures in quartz by combining the following dry-etching process either reactive ion etching (RIE) or inductively coupled plasma (ICP). A layer of gold film was coated on the quartz to act as a hard mask during the dry-etching process. A microhole array in quartz with a thin gold film covered on the surface was fabricated when choosing RIE. Each hole in the microhole array was surrounded with gold nanoparticle capped silica (Au/SiO₂) cones when using ICP instead of RIE. This is due to the thin gold film that serves as the mask for creating the surface roughness required for creating the silica cone structure.     

Fabrication of high-aspect-ratio silicon nanopillar arrays with the conventional reactive ion etching technique

We fabricate silicon nanopillar arrays with pillar diameters smaller than 200 nm by using the conventional reactive ion etching (RIE) technique and nickel masks. We use the ratio between the lateral and vertical etching rates as an estimate of the etching anisotropy. The dependence of this ratio on the rf power, the chamber pressure, and the gas mixture is investigated systematically to achieve the largest etching anisotropy. Using the optimized etching parameters in the RIE process, we demonstrate silicon pillars with smooth surface, vertical sidewalls, and aspect ratios higher than 20. In addition, we employ dilute aqua regia to treat the pillars and shrink the diameters to 70 nm. The pillar height remains ∼2500 nm after the treatment. PACS 52.77.Bn; 81.65.Cf; 85.40.Hp     

a-Si:H based two-dimensional photonic crystals

We describe the fabrication processes of silicon-based two-dimensional photonic crystals (2D-PCs) with a photonic band gap in the near-IR range. The procedures involve electron beam lithography followed by an anisotropic etching step of hydrogenated amorphous silicon thin films deposited by plasma enhanced chemical vapor deposition. Micrometric and submicrometric arrays of cylindrical holes are transferred using a poly-methylmethacrylate resist layer as a mask. A careful comparison between standard parallel plate reactive ion etching and inductively coupled plasma etching techniques is performed, aimed at obtaining periodic structures with high aspect ratio and good profile sharpness.