Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

150?快速热氮化SiO2膜的击穿特性

对具有器件质量的150?厚SiO₂膜经传统的长时间热氮化和高温快速热氮化后,研究了其击穿特性及其在高场强下的耐久力。研究结果表明,氮化后击穿场强的分布变窄,对栅电极面积的依赖性减弱,最大击穿场强略微下降。热氮化对高电场下SiO₂/Si界面稳定性和决定于时间的介质击穿均有改善。这种改善既取决于所加栅电压的极性,又强烈依赖于氮化工艺条件。根据电流传输机构,本文提出一种考虑了电荷积累、陷阱密度及其重心位置的击穿模型。 关键词：     

Negative bias-induced threshold voltage instability and zener/interface trapping mechanism in GaN-based MIS-HEMTs

We investigate the instability of threshold voltage in D-mode MIS-HEMT with in-situ SiN as gate dielectric under different negative gate stresses.The complex non-monotonic evolution of threshold voltage under the negative stress and during the recovery process is induced by the combination effect of two mechanisms.The effect of trapping behavior of interface state at SiN/AlGaN interface and the effect of zener traps in AlGaN barrier layer on the threshold voltage instability are opposite to each other.The threshold voltage shifts negatively under the negative stress due to the detrapping of the electrons at SiN/AlGaN interface,and shifts positively due to zener trapping in AlGaN barrier layer.As the stress is removed,the threshold voltage shifts positively for the retrapping of interface states and negatively for the thermal detrapping in AlGaN.However,it is the trapping behavior in the AlGaN rather than the interface state that results in the change of transconductance in the D-mode MIS-HEMT.     

基于脉冲方法的超短栅长GaN基高电子迁移率晶体管陷阱效应机理

陷阱效应导致的电流崩塌是制约GaN基微波功率电子器件性能提高的一个重要因素,研究深能级陷阱行为对材料生长和器件开发具有非常重要的意义.随着器件频率的提升,器件尺寸不断缩小,对小尺寸器件中深能级陷阱的表征变得越发困难.本文制备了超短栅长（L_g=80 nm）的AlGaN/GaN金属氧化物半导体高电子迁移率晶体管（MOSHEMT）,并基于脉冲I-V测试和二维数值瞬态仿真对器件的动态特性进行了深入研究,分析了深能级陷阱对AlGaN/GaN MOSHEMT器件动态特性的影响以及相关陷阱效应的内在物理机制.结果表明,AlGaN/GaN MOSHEMT器件的电流崩塌随着栅极静态偏置电压的增加呈非单调变化趋势,这是由栅漏电注入和热电子注入两种陷阱机制共同作用的结果.根据研究结果推断,可通过改善栅介质的质量以减小栅漏电或提高外延材料质量以减少缺陷密度等措施达到抑制陷阱效应的目的,从而进一步抑制电流崩塌.     

Room-temperature fabrication of ultra-thin ZrOx dielectric for high-performance InTiZnO thin-film transistors

In this letter, indium–titanium–zinc–oxide thin-film transistors with zirconium oxide (ZrO_x) gate dielectric were fabricated at room temperature. In the devices, an ultra-thin ZrO_x layer was formed as the gate dielectric by sol–gel process followed by ultraviolet (UV) irradiation. The devices can be operated under a voltage of 4 V. Enhancement mode operations with a high field-effect mobility of 48.9 cm²/V s, a threshold voltage of 1.4 V, a subthreshold swing of 0.2 V/decade, and an on/off current ratio of 10⁶ were realized. Our results demonstrate that UV-irradiated ZrO_x dielectric is a promising gate dielectric candidate for high-performance oxide devices.     

Degradation of gate-recessed MOS-HEMTs and conventional HEMTs under DC electrical stress

The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT) is compared with that of conventional high electron mobility transistor(HEMT) under direct current(DC) stress,and the degradation mechanism is studied. Under the channel hot electron injection stress, the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer, and that under the gate dielectric of the device. The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress, which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel. However, because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel, the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT. The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.     

Random telegraph noise on the threshold voltage of multi-level flash memory

We investigate the impact of random telegraph noise (RTN) on the threshold voltage of multi-level NOR flash memory. It is found that the threshold voltage variation (ΔV_th) and the distribution due to RTN increase with the programmed level (V_th) of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.     

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices

This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO₂. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO₂/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.     

Experimental demonstration of the time reversal Aharonov-Casher effect

We demonstrate the time reversal Aharonov-Casher (AC) effect in small arrays of mesoscopic semiconductor rings. By using an electrostatic gate we can control the spin precession rate and follow the AC phase over several interference periods. We show that we control the precession rate in two different gate voltage ranges; in the lower range the gate voltage dependence is strong and linear and in the higher range the dependence in almost an order of magnitude weaker. We also see the second harmonic of the AC interference, oscillating with half the period. We finally map the AC phase to the spin-orbit interaction parameter alpha and find it is consistent with Shubnikov-de Haas analysis.     

Long-term stability of InP MIS devices

Room-temperature bias stress measurements were performed on n-type InP MIS capacitors. A wide range of interface passivation processes and gate dielectrics was investigated. A generally observed behaviour under positive bias stress is a slow trapping - fast detrapping consistent with a trap distribution in the interfacial layer above the conduction band edge of InP. Large variations both in the magnitude and in the time dependence of the flat-band voltage shift ΔV_FB are observed. We discuss these drift behaviours in terms of interface traps - rather than bulk dielectric traps - in relation with the physico-chemical properties of the interface. It is shown that devices based on InP treated by annealing under arsenic pressure and controlled oxidation exhibit a very good stability. For any passivation procedure, the drift is strongly diminished if the device is stressed with AC voltage compared to DC voltage.     

Electron-phonon and electron-electron interactions in organic field effect transistors

Recent experiments have demonstrated that the performances of organic FETs strongly depend on the dielectric properties of the gate insulator. In particular, it has been shown that the temperature dependence of the mobility evolves from a metallic-like to an insulating behavior upon increasing the dielectric constant of the gate material. This phenomenon can be explained in terms of the formation of small polarons, due to the polar interaction of the charge carriers with the phonons at the organic/dielectric interface. Building on this model, the possible consequences of the Coulomb repulsion between the carriers at high concentrations are analyzed.     

Electric-field induced ion-leveraged metal–insulator transition in conducting polymer-based field effect devices

The field effect devices prepared completely from conducting polymers, especially poly(3,4-ethylenedioxythiophene)/poly(styrene sulfonic acid) (PEDOT/PSS), were studied. Normally in a conductive “on” state, the transistor-like device has a transition to a substantially less conductive “off” state at an applied positive gate voltage, typically ∼15–25 V. The current ratio I_off/I_on can exceed 10⁻⁴ at room temperature. We have found that the field effect is strongly temperature dependent and is substantially reduced upon decreasing the temperature by only a 10 °C. This loss of current reduction upon application of a gate voltage is not due to the temperature dependence of the electrical conductivity of polymers of which the devices are made. The temperature dependence of the dc conductivity of the PEDOT/PSS follows the variable range hopping law both before and after application of the gate voltage, though with an increased activation energy, T₀. We suggest that the conducting polymer is near the metal–insulator transition and that the field effect in the device is related to the electric field modulating this transition in the region underneath the gate electrode. The transition is controlled and leveraged by ion motion. The time dynamics of the current with the gate modulation strongly supports our conjecture. We demonstrate the generality of the phenomena by presenting similar results for devices fabricated from the conducting polypyrrole doped with Cl.     

Energy distribution extraction of negative charges responsible for positive bias temperature instability

A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability(PBTI) stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 e V above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.     

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

离子凝胶薄膜栅介石墨烯场效应管

在石墨烯场效应晶体管栅介结构中引入具有良好电容特性或极化特性的材料可改善晶体管性能.本文采用化学气相沉积制备的石墨烯并以PVDF-[EMIM]TF2N离子凝胶薄膜(ion-gel film)作为介质层制备底栅型石墨烯场效应管(graphene-based field effect transistor, GFET),研究其电学特性以及真空环境和温度对GFET性能的影响.结果表明离子凝胶薄膜栅介石墨烯场效应晶体管表现出良好的电学特性,室温空气环境中,与SiO_2栅介GFET相比, ion-gel膜栅介GFET开关比(J_(on)/J_(off))和跨导(g_m)分别提高至6.95和3.68×10~(–2) mS,而狄拉克电压(V_(Dirac))低至1.3 V;真空环境下ion-gel膜栅介GFET狄拉克电压最低可降至0.4 V;随着温度的升高, GFET的跨导最高可提升至6.11×10~(–2) mS.     

氢化非晶硅薄膜晶体管的低频噪声特性

针对氢化非晶硅薄膜晶体管(hydrogenated amorphous silicon thin film transistor,a-Si:H TFT)的低频噪声特性展开实验研究.由测量结果可知,a-Si:H TFT的低频噪声特性遵循1/f~γ(f为频率,γ≈0.92)的变化规律,主要受迁移率随机涨落效应的影响.基于与迁移率涨落相关的载流子数随机涨落模型(?N-?μ模型),在考虑源漏接触电阻、局域态俘获及释放载流子效应等情况时,对器件低频噪声特性随沟道电流的变化进行分析与拟合.基于a-Si:H TFT的亚阈区电流-电压特性提取器件表面能带弯曲量与栅源电压之间的关系,通过沟道电流噪声功率谱密度提取a-Si:H TFT有源层内局域态密度及其分布.实验结果表明:局域态在禁带内随能量呈e指数变化,两种缺陷态在导带底密度分别约为6.31×10~(18)和1.26×10~(18)cm~(-3)·eV~(-1),特征温度分别约为192和290 K,这符合非晶硅层内带尾态密度及其分布特征.最后提取器件的平均Hooge因子,为评价非晶硅材料及其稳定性提供参考.     

The role of the induction zone on the detonation–turbulence linear interaction

Detonation–turbulence linear interaction analysis extends the non-reactive shock–turbulence analog by considering geometrical scaling of the noise with respect to the half-reaction distance. The analysis emphasizes the effect of structure in energizing selective frequencies, and determining acoustic amplification in the farfield. Natural frequencies are determined as eigenvalues of the inviscid non-forced interaction problem. They modify postshock energy spectra by supporting resonant amplification, and cast light on the role of the activation energy on the detonation–turbulence interaction. Detonations with higher activation energies amplify smaller scales by resonant amplification. An analysis of the bifurcation parameters reveals a strong link between detonation overdrive and acoustic attenuation. The damping is correlated with the subcritical nature of the characteristic solutions for high overdrives. For detonation conditions on the stability boundary, a larger overdrive supports a weaker resonant peak in both the temperature and longitudinal velocity spectra. Postshock temperature variances feature a well-defined maximum within the reaction zone, which is found to be sensitive to changes in detonation structure.     

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors(NMOSFETs)is presented.In the process,a HfSiON gate dielectric with an equivalent oxide thickness of 10 A was prepared by a simple physical vapor deposition method.Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate.After the source/drain formation,the poly-Si dummy gate was removed by tetramethylammonium hydroxide(TMAH)wet-etching and replaced by a TaN metal gate.Because the metal gate was formed after the ion-implant doping activation process,the effects of the high temperature process on the metal gate were avoided.The fabricated device exhibits good electrical characteristics,including good driving ability and excellent sub-threshold characteristics.The device’s gate length is 73 nm,the driving current is 117μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μm.The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage(~0.24 V)for high performance NMOSFETs.The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.     

Structural and electrical performance of epitaxial InP based heterojunctions prepared by liquid phase epitaxy

Thin films of InP was grown on single crystalline substrates of Si to form InP/Si heterojunctions by liquid phase epitaxy (LPE) and its morphology and crystalline characteristics were achieved. The essential electrical properties and its main parameters were extracted using the current density-voltage. The analysis was done to obtain the rectification characteristics which has its maximum value at a certain voltage of 0.7 V. Moreover, the heterojunction obeys ohmic behavior followed by quadratic space charge limited conduction at lower and higher voltage regions, respectively. The conductivity under AC bias as well as the dielectric behaviors of the heterojunction was explored in the frequency range 100 kHz–5 MHz and in the temperature range 298–623 K. The AC conductivity is interpreted by the correlated barrier hopping model via single polaron with activation energy dependent on the applied frequency. The response of the dielectric constants confirms its remarkable dependence on both frequency and temperature.