Ni全硅化金属栅功函数调节技术研究

通过制备栅内不同掺杂条件的Ni全硅化金属栅电容并分析其C-V和V_fb-EOT特性发现,Ga和Yb较常规的杂质而言具有更好的栅功函数调节能力,能够分别将Ni全硅化金属栅电极功函数调节到价带顶和导带底附近,满足高性能体硅平面互补金属氧化物半导体(CMOS)器件对栅电极功函数的要求. 同时根据电偶极子(Dipole)理论分析了Ga和Yb具有较强栅功函数调节能力的原因. 另外,研究发现栅内掺入Ga或Yb杂质后的Ni全硅化金属栅电容的电容值变大、栅极泄漏电流反而变小,通过对C-V和栅极泄漏电流特性进行分析,对这一现象进行了解释. 关键词： 金属栅电极 功函数 硅化物     

A novel method for sacrificial layer release in MEMS devices fabrication

During the forming process of the free-standing structure or the functional cavity when releasing the high aspect ratio sacrificial layer,such structures tend to stick to the substrate due to capillary force.This paper describes the application of pull-in length conception as design rules to a novel ’dimpled’ method in releasing sacrificial layer.Based on the conception of pull-in length in adhering phenomenon,the fabrication and releasing sacrificial layer methods using micro bumps based on the silicon substrate were presented.According to the thermal isolation performances of one kind of micro electromechanical system device thermal shear stress sensor,the sacrificial layers were validated to be successfully released.     

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors(NMOSFETs)is presented.In the process,a HfSiON gate dielectric with an equivalent oxide thickness of 10 A was prepared by a simple physical vapor deposition method.Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate.After the source/drain formation,the poly-Si dummy gate was removed by tetramethylammonium hydroxide(TMAH)wet-etching and replaced by a TaN metal gate.Because the metal gate was formed after the ion-implant doping activation process,the effects of the high temperature process on the metal gate were avoided.The fabricated device exhibits good electrical characteristics,including good driving ability and excellent sub-threshold characteristics.The device’s gate length is 73 nm,the driving current is 117μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μm.The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage(~0.24 V)for high performance NMOSFETs.The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.     

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiO_x. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1(NH_4OH:H_2O_2:H_2O = 1 : 1 : 5) and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl_3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl_3/SF_6/O_2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl_3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.     

A novel anti-shock silicon etching apparatus for solving diaphragm release problems

This paper presents a novel anti-shock bulk silicon etching apparatus for solving a universal problem which occurs when releasing the diaphragm (e.g.\ SiNx), that the diaphragm tends to be probably cracked by the impact of heating-induced bubbles, the swirling of heating-induced etchant, dithering of the hand and imbalanced etchant pressure during the wafer being taken out. Through finite element methods, the causes of the diaphragm cracking are analysed. The impact of heating-induced bubbles could be the main factor which results in the failure stress of the SiNx diaphragm and the rupture of it. In order to reduce the four potential effects on the cracking of the released diaphragm, an anti-shock bulk silicon etching apparatus is proposed for using during the last etching process of the diaphragm release. That is, the silicon wafer is first put into the regular constant temperature etching apparatus or ultrasonic plus, and when the residual bulk silicon to be etched reaches near the interface of the silicon and SiNx diaphragm, within a distance of 50--80~\mu m (the exact value is determined by the thickness, surface area and intensity of the released diaphragm), the wafer is taken out carefully and put into the said anti-shock silicon etching apparatus. The wafer's position is at the geometrical centre, also the centre of gravity of the etching vessel. An etchant outlet is built at the bottom. The wafer is etched continuously, and at the same time the etchant flows out of the vessel. Optionally, two symmetrically placed low-power heating resistors are put in the anti-shock silicon etching apparatus to quicken the etching process. The heating resistors' power should be low enough to avoid the swirling of the heating-induced etchant and the impact of the heating-induced bubbles on the released diaphragm. According to the experimental results, the released SiNx diaphragm thus treated is unbroken, which proves the practicality of the said anti-shock bulk silicon etching apparatus.     

微波法合成S-苄基半胱氨酰甘氨酸乙酯

微波条件下,溴化氢醋酸对S-苄基-N-苄氧羰基半胱氨酰甘氨酸乙酯(1)进行脱保护反应,合成了S-苄基半胱氨酰甘氨酸乙酯(2).最佳反应条件为:1 2.9 mmol,n(1):n(HBr-AcOH)=1:6,微波功率200 W,于30 ℃辐射20 min,2的收率为87%.其结构经~1H NMR和IR表征.     

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride (HfSiON) on ultrathin SiO₂ buffer layer. The gate dielectric with 10? (1?= 0.1 nm) equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant (k=14) and low gate-leakage current (I_g=1.9×10^-3A/cm² @V_g=V_fb-1V for EOT of 10?). TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.     

微纳加工技术在微纳电子器件领域的应用

微纳加工技术推动着集成电路不断缩小器件尺寸和提高集成度，光学光刻技术依然是目前的主流微纳加工技术，同时有多种替代技术如电子束直写、极紫外光刻和投影电子束技术，文章介绍了自上而下的微纳加工技术的进展及其在微纳器件研制的重要作用。