A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors(NMOSFETs)is presented.In the process,a HfSiON gate dielectric with an equivalent oxide thickness of 10 A was prepared by a simple physical vapor deposition method.Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate.After the source/drain formation,the poly-Si dummy gate was removed by tetramethylammonium hydroxide(TMAH)wet-etching and replaced by a TaN metal gate.Because the metal gate was formed after the ion-implant doping activation process,the effects of the high temperature process on the metal gate were avoided.The fabricated device exhibits good electrical characteristics,including good driving ability and excellent sub-threshold characteristics.The device’s gate length is 73 nm,the driving current is 117μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μm.The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage(~0.24 V)for high performance NMOSFETs.The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.     

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiO_x. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1(NH_4OH:H_2O_2:H_2O = 1 : 1 : 5) and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl_3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl_3/SF_6/O_2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl_3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.     

双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.     

基于蛋清栅介质的超低压双电层薄膜晶体管

新一代环保、生物兼容性电子功能器件受到了广泛关注.本文采用具有高质子导电特性的天然鸡蛋清作为耦合电解质膜制备双电层薄膜晶体管,该薄膜晶体管以氧化铟锡导电玻璃为衬底和底电极,以旋涂法制备的鸡蛋清为栅介质,以磁控溅射沉积的氧化铟锌为沟道和源漏电极.实验结果表明,这种基于鸡蛋清的栅介质具有良好的绝缘性,并能在其与沟道界面处形成巨大的双电层电容,从而使得该类晶体管具有超低工作电压（1.5 V）、低亚阈值（164 mV/dec）、大电流开关比（2.4×10⁶）和较高的饱和区场效应迁移率（38.01 cm²/（V· s））.这种以天然鸡蛋清为栅介质的超低压双电层TFTs有望应用于新型生物电子器件及低能耗便携式电子产品.     

离子凝胶薄膜栅介石墨烯场效应管

在石墨烯场效应晶体管栅介结构中引入具有良好电容特性或极化特性的材料可改善晶体管性能.本文采用化学气相沉积制备的石墨烯并以PVDF-[EMIM]TF2N离子凝胶薄膜(ion-gel film)作为介质层制备底栅型石墨烯场效应管(graphene-based field effect transistor, GFET),研究其电学特性以及真空环境和温度对GFET性能的影响.结果表明离子凝胶薄膜栅介石墨烯场效应晶体管表现出良好的电学特性,室温空气环境中,与SiO_2栅介GFET相比, ion-gel膜栅介GFET开关比(J_(on)/J_(off))和跨导(g_m)分别提高至6.95和3.68×10~(–2) mS,而狄拉克电压(V_(Dirac))低至1.3 V;真空环境下ion-gel膜栅介GFET狄拉克电压最低可降至0.4 V;随着温度的升高, GFET的跨导最高可提升至6.11×10~(–2) mS.     

Ta和TaN底电极对原子层淀积HfO2介质MIM电性能的影响

以Ta,TaN为衬底,采用原子层淀积方法制备高介电常数HfO₂介质,比较研究了不同衬底电极对金属-绝缘体-金属（MIM）电容的性能影响.结果表明,采用TaN底电极能够获得较高的电容密度和较小的电容电压系数（VCC）,在1MHz下的其电容密度为7.47fF/μm²,VCC为356ppm/V²和493ppm/V,这归因于TaN底电极与HfO₂介质之间良好的界面特性.两种电容在3?V时漏电流为5×10^-8关键词： 高介电常数 MIM电容 2薄膜')" href="#">HfO₂薄膜 电极     

High density Al2O3/TaN-based metal--insulator-- metal capacitors in application to radio frequency integrated circuits

Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.     

Impacts of Ti on electrical properties of Ge metal–oxide–semiconductor capacitors with ultrathin high-k LaTiON gate dielectric

Ge Metal–Oxide–Semiconductor (MOS) capacitors with LaON gate dielectric incorporating different Ti contents are fabricated and their electrical properties are measured and compared. It is found that Ti incorporation can increase the dielectric permittivity, and the higher the Ti content, the larger is the permittivity. However, the interfacial and gate-leakage properties become poorer as the Ti content increases. Therefore, optimization of Ti content is important in order to obtain a good trade-off among the electrical properties of the device. For the studied range of the Ti/La₂O₃ ratio, a suitable Ti/La₂O₃ ratio of 14.7% results in a high relative permittivity of 24.6, low interface-state density of 3.1×10¹¹ eV⁻¹ cm⁻², and relatively low gate-leakage current density of 2.0×10⁻³ A cm⁻² at a gate voltage of 1 V.     

Characterization of gadolinium oxide film by pulse laser deposition

In this work, Gd-oxide dielectric films were deposited on Si by pulse laser deposition method (PLD), moreover, the micro-structures and electrical properties were reported. High-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) indicated that Gd-oxide was polycrystalline Gd₂O₃ structure, and no Gd metal phase was detected. In addition, both interface at Si and Ni fully silicide (FUSI) gate were smooth without the formation of Si-oxide. X-ray photoelectron spectroscopy (XPS) confirmed the formation of Gd₂O₃ and gave an atom ratio of 1:1 for Gd:O, indicating O vacancies existed in Gd₂O₃ polycrystal matrix even at O₂ partial pressure of 20 mTorr. Electrical measurements indicated that the dielectric constant of Gd-oxide film was 6 and the leakage current was 0.1 A/cm² at gate bias of 1 V.     

Enhanced electrical properties of pentacene-based organic thin-film transistors by modifying the gate insulator surface

A reliable surface treatment for the pentacene/gate dielectric interface was developed to enhance the electrical transport properties of organic thin-film transistors (OTFTs). Plasma-polymerized fluorocarbon (CFx) film was deposited onto the SiO₂ gate dielectric prior to pentacene deposition, resulting in a dramatic increase of the field-effect mobility from 0.015 cm²/(V s) to 0.22 cm²/(V s), and a threshold voltage reduction from −14.0 V to −9.9 V. The observed carrier mobility increase by a factor of 10 in the resulting OTFTs is associated with various growth behaviors of polycrystalline pentacene thin films on different substrates, where a pronounced morphological change occurs in the first few molecular layers but the similar morphologies in the upper layers. The accompanying threshold voltage variation suggests that hole accumulation in the conduction channel-induced weak charge transfer between pentacene and CFx.     

Synthesis,characterization and radiation damage studies of high-k dielectric (HfO2) films for MOS device applications

The current trend in miniaturization of metal oxide semiconductor devices needs high-k dielectric materials as gate dielectrics. Among all the high-k dielectric materials, HfO₂ enticed the most attention, and it has already been introduced as a new gate dielectric by the semiconductor industry. High dielectric constant (HfO₂) films (10?nm) were deposited on Si substrates using the e-beam evaporation technique. These samples were characterized by various structural and electrical characterization techniques. Rutherford backscattering spectrometry, X-ray reflectivity, and energy-dispersive X-ray analysis measurements were performed to determine the thickness and stoichiometry of these films. The results obtained from various measurements are found to be consistent with each other. These samples were further characterized by I–V (leakage current) and C–V measurements after depositing suitable metal contacts. A significant decrease in the leakage current and the corresponding increase in device capacitance are observed when these samples were annealed in oxygen atmosphere. Furthermore, we have studied the influence of gamma irradiation on the electrical properties of these films as a function of the irradiation dose. The observed increase in the leakage current accompanied by changes in various other parameters, such as accumulation capacitance, inversion capacitance, flat band voltage, mid-gap voltage, etc., indicates the presence of various types of defects in irradiated samples.     

具有高开启/关断电流比的Al2O3/AlGaN/GaN金属氧化物半导体高电子迁移率晶体管

采用原子层淀积(ALD)方法,制备了Al₂O₃为栅介质的高性能AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT)。在栅压为-20 V时,MOS-HEMT的栅漏电比Schottky-gate HEMT的栅漏电低4个数量级以上。在栅压为+2 V时,Schottky-gate HEMT的栅漏电为191μA;在栅压为+20 V时,MOS-HEMT的栅漏电仅为23.6 nA,比同样尺寸的Schottky-gate HEMT的栅漏电低将近7个数量级。AlGaN/GaN MOS-HEMT的栅压摆幅达到了±20 V。在栅压V_gs=0 V时, MOS-HEMT的饱和电流密度达到了646 mA/mm,相比Schottky-gate HEMT的饱和电流密度(277 mA/mm)提高了133%。栅漏间距为10μm的AlGaN/GaN MOS-HEMT器件在栅压为+3 V时的最大饱和输出电流达到680 mA/mm,特征导通电阻为1.47 mΩ·cm²。Schottky-gate HEMT的开启与关断电流比仅为10⁵,MOS-HEMT的开启与关断电流比超过了10⁹,超出了Schottky-gate HEMT器件4个数量级,原因是栅漏电的降低提高了MOS-HEMT的开启与关断电流比。在V_gs=-14 V时,栅漏间距为10μm的AlGaN/GaN MOS-HEMT的关断击穿电压为640 V,关断泄露电流为27μA/mm。     

Influence of Si/SiO2 interface properties on electrical performance and breakdown characteristics of ultrathin stacked oxide/nitride dielectric films

In this work, the influence of Si/SiO₂ interface properties, interface nitridation and remote-plasma-assisted oxidation (RPAO) thickness (<1 nm), on electrical performance and TDDB characteristics of sub-2 nm stacked oxide/nitride gate dielectrics has been investigated using a constant voltage stress (CVS). It is demonstrated that interfacial plasma nitridation improves the breakdown and electrical characteristics. In the case of PMOSFETs stressed in accumulation, interface nitridation suppresses the hole traps at the Si/SiO₂ interface evidenced by less negative V_t shifts. Interface nitridation also retards hole tunneling between the gate and drain, resulting in reduced off-state drain leakage. In addition, the RPAO thickness of stacked gate dielectrics shows a profound effect in device performance and TDDB reliability. Also, it is demonstrated that TDDB characteristics are improved for both PMOS and NMOS devices with the 0.6 nm-RPAO layer using Weibull analysis. The maximum operating voltage is projected to be improved by 0.3 V difference for a 10-year lifetime. However, physical breakdown mechanism and effective defect radius during stress appear to be independent of RPAO thickness from the observation of the Weibull slopes. A correlation between trap generation and dielectric thickness changes based on the C-V distortion and oxide thinning model is presented to clarify the trapping behavior in the RPAO and bulk nitride layer during CVS stress.     

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

Effects of barium on the nonlinear electrical characteristics and dielectric properties of SnO2-based varistors

The effects of barium on electrical and dielectric properties of the SnO_2·Co_2O_3·Ta_2O_5 varistor system sintered at 1250℃ for 60min were investigated. It is found that barium significantly improves the nonlinear properties. The breakdown electrical field increases from 378.0 to 2834.5V/mm, relative dielectric constant (at 1kHz) falls from 1206 to 161 and the resistivity (at 1kHz) rises from 60.3 to 1146.5kΩ·cm with an increase of BaCO_3 concentration from 0mol% to 1.00mol%. The sample with 1.00mol% barium has the best nonlinear electrical property and the highest nonlinear coefficient (α=29.2). A modified defect barrier model is introduced to illustrate the grain-boundary barrier formation of barium-doped SnO_{2}-based varistors.     

低工作电压聚噻吩薄膜晶体管

以高掺杂Si单晶片作为衬底且充当栅电极,采用磁控溅射法在硅片上沉积HfTiO薄膜作为栅介质层,聚三己基噻吩(P3HT)薄膜作为半导体活性层,金属Au作为源、漏电极,并采用十八烷基三氯硅烷(OTS)对栅介质层表面修饰,在空气环境下成功地制备出聚合物薄膜晶体管(PTFT).PTFT器件测试结果表明,该晶体管在低的驱动电压(<-1 V)下仍呈现出良好的饱和行为,其阈值电压和有效场效应迁移率分别为0.4 V和2.2×10^-2 cm²/V ·s.通过对金属-聚合物-氧化物 关键词： 聚合物薄膜晶体管 聚三己基噻吩 场效应迁移率 k栅介质')" href="#">高k栅介质     

LaTiO高k栅介质Ge MOS电容电特性及Ti含量优化

采用共反应溅射法将Ti添加到La_2O_3中,制备了LaTiO/Ge金属-氧化物-半导体电容,并就Ti含量对器件电特性的影响进行了仔细研究.由于Ti-基氧化物具有极高的介电常数,LaTiO栅介质能够获得高k值;然而由于界面/近界面缺陷随着Ti含量的升高而增加,添加Ti使界面质量恶化,进而使栅极漏电流增大、器件可靠性降低.因此,为了在器件电特性之间实现协调,对Ti含量进行优化显得尤为重要.就所研究的Ti/La_2O_3比率而言,18.4%的Ti/La_2O_3比率最合适.该比率导致器件呈现出高k值(22.7)、低D_(it)(5.5×10~(11)eV~(-1)·cm~(-2))、可接受的J_g(V_g=1V,J_g=7.1×10~(-3)A·cm~(-2))和良好的器件可靠性.     

Surface and electrical properties of organic-inorganic hybrid structure as gate insulator to organic thin film transistor

Carbon-based OTFT devices were fabricated using a plasma process for the gate electrode and gate insulators. A nanocrystalline carbon (nc-C) film was used as the gate electrode, and three different layers, cyclohexene, diamond-like carbon (DLC), and cyclohexene/DLC (hybrid insulator), were used as the gate insulator. The surface and electrical properties of the three different gate insulators on the nc-C gate electrode were investigated using the SPM method, and the leakage current density and dielectric constant of the metal-insulator-metal (MIM) structures with three different insulator layers were evaluated. The hybrid insulator layer had a very smooth surface, approximately 0.2 nm, a uniform surface without defects, and good adhesion between the layers. Overall, it is believed that the hybrid insulator lead to a decrease in the electrical leakage current and an improvement in the device performance.