Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional (3D) TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor (NMOS) transistor or P-channel metal-oxide semiconductor (PMOS) transistor can mitigate the cross section of single event upset (SEU) in 14-nm complementary metal-oxide semiconductor (CMOS) bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Unlike dual-interlock cell (DICE) design, this approach is more effective under heavy ion irradiation of higher LET, in the presence of enough taps to ensure the rapid recovery of well potential. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.     

90 nm CMOS工艺下p+深阱掺杂浓度对电荷共享的影响

基于3维TCAD器件模拟,研究了90 nm CMOS双阱工艺下p⁺深阱掺杂对电荷共享的影响. 研究结果表明:改变p⁺深阱的掺杂浓度对PMOS管之间的电荷共享的影响要远大于NMOS管;通过增加p⁺深阱的掺杂浓度可以有效抑制PMOS管之间的电荷共享. 这一结论可用于指导电荷共享的加固. 关键词： 电荷共享 单粒子效应 +深阱掺杂')" href="#">p⁺深阱掺杂 双极晶体管效应     

The effect of substrate doping on the flatband and threshold voltages of a strained-Si pMOSFET

The effect of substrate doping on the flatband and threshold voltages of a strained-Si/SiGe p metal-oxide semiconductor field-effect transistor(pMOSFET) has been studied.By physically deriving the models of the flatband and threshold voltages,which have been validated by numerical simulation and experimental data,the shift in the plateau from the inversion region to the accumulation region as the substrate doping increases has been explained.The proposed model can provide a valuable reference to the designers of strained-Si devices and has been implemented in software for extracting the parameters of a strained-Si MOSFET.     

Effect of substrate doping on the flatband and threshold voltages of strained-Si pMOSFET

The effect of substrate doping on the flatband and threshold voltages of strained-Si/SiGe p metal-oxide semiconductor field-effect transistor (pMOSFET) has been studied. By physically deriving the models of the flatband and threshold voltages, which have been validated by numerical simulation and experimental data, the shift in the plateau from the inversion region to the accumulation region as the substrate doping increases has been explained. The proposed model can provide valuable reference to the designers of strained-Si devices and has been implemented in software for extracting the parameters of strained-Si MOSFET.     

The dual role of multiple-transistor charge sharing collection in single-event transients

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients (SETs) due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal-oxide semiconductor field-effect transistor (PMOS FET), but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

In this paper, the effect of floating body effect(FBE) on a single event transient generation mechanism in fully depleted(FD) silicon-on-insulator(SOI) technology is investigated using three-dimensional technology computer-aided design(3DTCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect(FBE) whether for positive or negative channel metal oxide semiconductor(PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking(IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.     

Temperature dependence of single event transient in 90-nm CMOS dual-well and triple-well NMOSFETs

This paper investigates the temperature dependence of single event transient (SET) in 90-nm complementary metat-oxide semiconductor (CMOS) dual-well and triple-well negative metal-oxide semiconductor field-effect transistors (NMOSFETs). Technology computer-aided design (TCAD) three-dimensional (3D) simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from -55℃ to 125℃, which is closely correlated with the source of NMOSFETs. This reveals that the pulse width increases with temperature in dual-well due to the weakening of anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

A novel LDMOS with a junction field plate and a partial N-buried layer

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with a high breakdown voltage (BV) and low specific on-resistance (R_on.sp) is proposed and investigated by simulation. It features a junction field plate (JFP) over the drift region and a partial N-buried layer (PNB) in the P-substrate. The JFP not only smoothes the surface electric field (E-field), but also brings in charge compensation between the JFP and the N-drift region, which increases the doping concentration of the N-drift region. The PNB reshapes the equipotential contours, and thus reduces the E-field peak on the drain side and increases that on the source side. Moreover, the PNB extends the depletion width in the substrate by introducing an additional vertical diode, resulting in a significant improvement on the vertical BV. Compared with the conventional LDMOS with the same dimensional parameters, the novel LDMOS has an increase in BV value by 67.4%, and a reduction in R_on.sp by 45.7% simultaneously.     

Three-dimensional simulation of fabrication process-dependent effects on single event effects of SiGe heterojunction bipolar transistor

The fabrication process dependent effects on single event effects(SEEs) are investigated in a commercial silicon–germanium heterojunction bipolar transistor(SiGe HBT) using three-dimensional(3D) TCAD simulations. The influences of device structure and doping concentration on SEEs are discussed via analysis of current transient and charge collection induced by ions strike. The results show that the SEEs representation of current transient is different from representation of the charge collection for the same process parameters. To be specific, the area of C/S junction is the key parameter that affects charge collection of SEE. Both current transient and charge collection are dependent on the doping of collector and substrate. The base doping slightly influences transient currents of base, emitter, and collector terminals. However, the SEEs of SiGe HBT are hardly affected by the doping of epitaxial base and the content of Ge.     

ESD protection for the tolerant I/O circuits using PESD implantation

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call “PESD” implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25 μm process, this method provides a significant improvement in the cascode ESD performance.     

单粒子瞬变中的双极放大效应研究

采用三维数值模拟的方法对比研究了单个NMOS晶体管和反相器链中的单粒子瞬变（single event transient,SET）电流脉冲,发现深亚微米工艺下双极放大电流在单管的SET电流脉冲中占主要成分,而在反相器链的SET模拟中不明显,分析二者的区别解释了源/体结偏压的形成过程和放大机理,并证明了双极放大效应受源/体结偏压影响的结论.在此基础上分析了NMOS管中源极的正向电流及其机理,发现台阶区的源极正向电流主要是由扩散作用形成的. 关键词： 单粒子瞬变 双极放大 混合模拟 台阶区电流     

Spintronic with semiconductors

Soon afterwards the discovery of the giant magnetoresistance in metallic multilayers, researchers have attempted to integrate spintronic properties with semiconductor materials. They came up against several difficulties related to the structural and electronic properties of the ferromagnetic metal-semiconductor interface. We will report on the recent progress made in this field of spintronic with semiconductors. First of all we will explain the interfacial resistance conditions required to inject and detect efficient spin current in a semiconductor and in a second part we will show that efficient spin injection experiments have been now achieved thanks to the addition of a tunnel resistance at the interface. We will then report on the magnetoresistance experiment performed with diluted magnetic semiconductors as ferromagnetic material. This type of material can constitute an alternative road to achieving electrical control spintronic devices. Finally, we will finish by reporting on research for a highly spin-polarized source to inject spin-polarized current in a semiconductor. It will be mainly focused on tunnel magnetoresistance junctions with semiconductor barriers and hot electron transistor. To cite this article: J.-M. George et al., C. R. Physique 6 (2005).     

势垒硅掺杂对GaN基LED极化电场及其光电性能的影响

势垒硅掺杂对InGaN量子阱中的电场及LED器件的光电性能有着重要的影响。采用6×6 K·P方法计算了不同势垒硅掺杂浓度对量子阱中电场的变化,研究表明当势垒硅掺杂浓度>1e¹⁸ cm^-3时,阱垒界面处的电场强度会变大,这主要是由于硅掺杂浓度过高导致量子阱中界面电荷的聚集。进一步发现随着势垒掺杂浓度的升高,总非辐射复合随之增加,其中俄歇复合增加,而肖克莱-霍尔-里德复合随之减少,这是由于点陷阱的增大形成了缺陷能级。电流电压曲线表明势垒掺杂可有效改善GaN基LED的工作电压,这归于掺杂浓度的提高改善了载流子的传输特性。当掺杂浓度为1e¹⁸ cm^-3时,获得了较高的内量子效率,这主要是由于适当的势垒掺杂降低了量子阱中界面电荷的损耗。     

Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology

This paper studies the total ionizing dose radiation effects on MOS (metal-oxide-semiconductor) transistors with normal and enclosed gate layout in a standard commercial CMOS (compensate MOS) bulk process. The leakage current, threshold voltage shift, and transconductance of the devices were monitored before and after $\gamma $-ray irradiation. The parameters of the devices with different layout under different bias condition during irradiation at different total dose are investigated. The results show that the enclosed layout not only effectively eliminates the leakage but also improves the performance of threshold voltage and transconductance for NMOS (n-type channel MOS) transistors. The experimental results also indicate that analogue bias during irradiation is the worst case for enclosed gate NMOS. There is no evident different behaviour observed between normal PMOS (p-type channel MOS) transistors and enclosed gate PMOS transistors.     

22 nm工艺超薄体全耗尽绝缘体上硅晶体管单粒子瞬态效应研究

利用计算机辅助设计技术数值仿真工具, 研究22 nm工艺技术节点下超薄体全耗尽绝缘体上硅晶体管单粒子瞬态效应, 系统地分析了掺杂地平面技术、重离子入射位置、栅功函数和衬底偏置电压对于单粒子瞬态效应的影响. 模拟结果表明, 掺杂地平面和量子效应对于单粒子瞬态效应影响很小, 重离子入射产生大量电荷, 屏蔽了初始电荷分布的差异性. 单粒子瞬态效应以及收集电荷和重离子入射位置强相关, 超薄体全耗尽绝缘体上硅最敏感的区域靠近漏端. 当栅功函数从4.3 eV变化到4.65 eV时, 单粒子瞬态电流峰值从564 μA减小到509 μA, 收集电荷从4.57 fC减小到3.97 fC. 超薄体全耗尽绝缘体上硅器件单粒子瞬态电流峰值被衬底偏置电压强烈调制, 但是收集电荷却与衬底偏置电压弱相关. 关键词： 超薄体全耗尽绝缘体上硅 单粒子瞬态效应 电荷收集 数值仿真     

锗硅异质结晶体管单粒子效应激光微束模拟

对国产锗硅异质结双极晶体管(SiGe HBT)进行了单粒子效应激光微束辐照试验,观测SiGe HBT单粒子效应的敏感区域,测试不同外加电压和不同激光能量下SiGe HBT集电极瞬变电流和电荷收集情况,并结合器件结构对试验结果进行分析。试验结果表明:国产SiGe HBT位于集电极/衬底结内的区域对单粒子效应敏感,波长为1064 nm的激光在能量约为1.5 nJ时诱发SiGe HBT单粒子效应,引起电流瞬变。入射激光能量增强,电流脉冲增大,电荷收集量增加;外加电压增大,电流脉冲的波峰增大;SiGe HBT的单粒子效应与外加电压大小和入射激光能量都相关,电压主要影响瞬变电流的峰值,而电荷收集量主要依赖于入射激光能量。     

漏致势垒降低效应对短沟道应变硅金属氧化物半导体场效应管阈值电压的影响

结合应变硅金属氧化物半导体场效应管(MOSFET)结构,通过求解二维泊松方程,得到了应变Si沟道的电势分布,并据此建立了短沟道应变硅NMOSFET的阈值电压模型.依据计算结果,详细分析了弛豫Si_1－βGe_β中锗组分β、沟道长度、漏电压、衬底掺杂浓度以及沟道掺杂浓度对阈值电压的影响,从而得到漏致势垒降低效应对小尺寸应变硅器件阈值电压的影响,对应变硅器件以及电路的设计具有重要的参考价值. 关键词： 应变硅金属氧化物半导体场效应管 漏致势垒降低 二维泊松方程 阈值电压模型     

Mg,Al掺杂对LiCoO2体系电子结构影响的第一原理研究

为了研究Mg ,Al掺杂对锂二次电池正极材料LiCoO2 体系的电子结构的影响 ,进而揭示Mg掺杂的LiCoO2 具有高电导率的机理 ,对Li(Co ,Al)O2 和Li(Co,Mg)O2 进行了基于密度泛函理论的第一原理研究 .通过对能带及态密度的分析 ,发现在Mg掺杂后价带出现电子态空穴 ,提高了电导 ,并且通过歧化效应 (disproportionation)改变了Co 3d电子在各能级的分布 ,而Al掺杂则没有这些作用 .O2 - 的离子性在掺杂后明显增强 .