Corner effects in double-gate/gate-all-around MOSFETs

Two kinds of corner effects existing in double-gate (DG) and gate-all-around (GAA) MOSFETs have been investigated by three-dimensional (3D) and two-dimensional (2D) simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL (drain induced barrier lowering) effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.     

HOT-CARRIER GENERATION MECHANISM AND HOT-CARRIER EFFECT IMMUNITY IN DEEP-SUB-MICRON GROOVED-GATE PMOSFETS

Based on the hydrodynamic energy transport model, immunity from the hot-carrier effect in deep-sub-micron grooved-gate p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) is analysed. The results show that hot carriers generated in grooved-gate PMOSFETs are much smaller than those in planar ones, especially for the case of channel lengths lying in the deep-sub-micron and super deep-sub-micron regions. Then, the hot-carrier generation mechanism and the reason why grooved-gate MOS devices can suppress the hot-carrier effect are studied from the viewpoint of physical mechanisms occurring in devices. It is found that the highest hot-carrier generating rate is at a medium gate bias voltage in three stress areas, similar to conventional planar devices. In deep-sub-micron grooved-gate PMOSFETs, the hot-carrier injection gate current is still composed mainly of the hot-electron injection current, and the hole injection current becomes dominant only at an extremely high gate voltage. In order to investigate other influences of the hot-carrier effect on the device characteristics, the degradation of the device performance is studied for both grooved-gate and planar devices at different interface states. The results show that the drift of the device electrical performance induced by the interface states in grooved-gate PMOSFETs is far larger than that in planar devices.     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

新型槽栅PMOSFET热载流子退化机理与抗热载流子效应研究

分析了槽栅器件中的热载流子形成机理,发现在三个应力区中,中栅压附近热载流子产生概率达到最大.利用先进的半导体器件二维器件仿真器研究了槽栅和平面PMOSFET的热载流子特 性,结果表明槽栅器件中热载流子的产生远少于平面器件,且对于栅长在深亚微米和超深亚 微米情况下尤为突出.为进一步探讨热载流子加固后对器件特性的其他影响,分别对不同种 类和浓度的界面态引起的器件栅极和漏极特性的漂移进行了研究,结果表明同样种类和密度 的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件.为开展深亚微米和亚0.1微米 新型槽栅 关键词： 槽栅PMOSFET 热载流子退化机理 热载流子效应     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si_{1 - X}Ge_X layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.     

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

Performance and analytical modelling of halo-doped surrounding gate MOSFETs

Halo structure is added to sub-100 nm surrounding-gate metal-oxide-semiconductor fieldeffect-transistors （MOS- FETs） to suppress short channel effect. This paper develops the analytical surface potential and threshold voltage models based on the solution of Poisson＇s equation in fully depleted condition for symmetric halo-doped cylindrical surrounding gate MOSFETs. The performance of the halo-doped device is studied and the validity of the analytical models is verified by comparing the analytical results with the simulated data by three dimensional numerical device simulator Davinci. It shows that the halo doping profile exhibits better performance in suppressing threshold voltage roll-off and drain-induced barrier lowering, and increasing carrier transport efficiency. The derived analytical models are in good agreement with Davinci.     

Tradeoff between speed and static power dissipation of ultra-thin body SOI MOSFETs

The speed performance and static power dissipation of the ultra-thin-body (UTB) MOSFETs have been comprehensively investigated, with both DC and AC behaviours considered. Source/drain extension width ($L_{\rm sp})$ and silicon film thickness $(t_{\rm si})$ are two independent parameters that influence the speed and static power dissipation of UTB silicon-on-insulator (SOI) MOSFETs respectively, which can result in great design flexibility. Based on the different effects of physical and geometric parameters on device characteristics, a method to alleviate the contradiction between power dissipated and speed of UTB SOI MOSFETs is proposed. The optimal design regions of $t_{\rm si}$ and $L_{\rm sp}$ for low operating power and high performance logic applications are given, which may shed light on the design of UTB SOI MOSFETs.     

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate(DM-DG) strained Si(s-Si) metal–oxide semiconductor field effect transistors(MOSFETs) are presented. The surface potential and the surface electric field expressions have been obtained by solving Poisson's equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate(SM-DG) MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.     

Influence of structural parameters on the immunity of short-channel effects in grooved-gate nMOSFET

This paper presents the influences of structural parameters on the immunity of short-channel effects in grooved-gate n-channel metal－oxide－semiconductor field effect transistor (nMOSFET) using the simulator PISCES-II. The zero or negative groove-junction depth is beneficial to the improvement of the threshold characters, but there exists a limited range. The doping concentration of both substrate and channel has a significant influence on the threshold characters as well as on the device transconductance. Thus, the variation in these adjustable parameters may help to optimize the device design.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.     

Fabrication of Ge-channel MOSFETs by using replacement gate process and selective epitaxial growth

We fabricated Ge-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by using replacement gate process and selective epitaxial growth. In our method, thin Ge layers were selectively grown on the channel region of MOSFETs after the removal of a sacrificial gate stack structure and the etching of the channel region. Ge layers with a smooth surface and a good morphology could be obtained by using the thin Si_0.5Ge_0.5 buffer layer. Dislocations were observed in the epitaxial layers and near the interface between the epitaxial layer and the substrates. We consider that these dislocations degrade the device performance. Although the electrical characteristics of the obtained MOSFETs need further improvement, our method is one of the promising candidates for the practical fabrication process of Ge-channel MOSFETs.     

A continuous analytic channel potential solution to doped symmetric double-gate MOSFETs from the accumulation to the strong-inversion region

A continuous yet analytic channel potential solution is proposed for doped symmetric double-gate (DG) MOSFETs from the accumulation to the strong-inversion region. Analytical channel potential relationship is derived from the complete 1-D Poisson equation physically, and the channel potential solution of the DG MOSFET is obtained analytically. The extensive comparisons between the presented solution and the numerical simulation illustrate that the solution is not only accurate and continuous in the whole operation regime of DG MOSFETs, but also valid to wide doping concentration and various geometrical sizes, without employing any fitting parameter.     

A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs

In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel-effects (SCEs) and improve the subthreshold performances for nanoelectronics applications. The model predicts a shift, increasing potential barrier, in the surface potential profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects. In the proposed structure, the subthreshold current and subthreshold swing characteristics are greatly improved in comparison with the conventional DG MOSFETs. The developed approaches are verified and validated by the good agreement found with the numerical simulation. (GCGS) DG MOSFET can alleviate the critical problem and further improve the immunity of SCEs of CMOS-based devices in the nanoscale regime.     

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.     

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.     

微米量级表面结构形貌特性对二次电子发射抑制的优化

抑制二次电子倍增效应是提高空间大功率微波器件和粒子加速器等设备性能的重要课题,而使用表面处理降低材料的二次电子发射系数是抑制二次电子倍增的有效手段.为优化寻找抑制效果最好的表面形貌,本文采用蒙特卡罗方法模拟了各种微米量级不同表面形貌的二次电子发射特性,研究占空比、深宽比、结构形状及排列方式等的影响.模拟结果表明,正方形、圆形、三角形凸起和凹陷结构的二次电子发射系数随占空比和深宽比的增大而减小,但存在饱和值;凸起结构的排列方式对二次电子发射系数的影响不大,但是凸起结构形状却对二次电子发射系数的影响较大,其中三角形的抑制效果最佳.对凹陷结构而言,不同形状的抑制效果差别不大;同时,占空比和深宽比相同时,凸起结构较凹陷结构抑制效果更佳.究其原因,核心在于垂直侧壁的“遮挡效应”,凹陷结构遮挡效应的大小与“陷阱”垂直高度有关,而凸起结构遮挡效应的大小和凸起部分的斜方向投影大小有关.     

Silicon-on-nothing MOSFETs fabricated with hydrogenand helium co-implantation

In this paper, a method to fabricate Silicon-on-Nothing (SON) MOSFETs using H$^{ + }$ and He$^{ + }$ co-implantation is presented. The technique is compatible with conventional CMOS technology and its feasibility has been experimentally demonstrated. SON MOSFETs with 50nm gate length have been fabricated. Compared with the corresponding bulk MOSFETs, the SON MOSFETs show higher on current, reduced leakage current and lower subthreshold slope.