Formation of the intermediate semiconductor larger for the Ohmic contact to silicon carbide using Germanium implantation

By formation of an intermediate semiconductor layer (ISL) with a narrow band gap at the metallic contact/SiC interface, this paper realises a new method to fabricate the low-resistance Ohmic contacts for SiC. An array of transfer length method (TLM) test patterns is formed on N-wells created by P+ ion implantation into Si-faced p-type 4H-SiC epilayer. The ISL of nickel-metal Ohmic contacts to n-type 4H-SiC could be formed by using Germanium ion implantation into SiC. The specific contact resistance ρc as low as 4.23×10-5 Ω·cm2 is achieved after annealing in N2 at 800 ℃ for 3 min, which is much lower than that (> 900℃) in the typical SiC metallisation process. The sheet resistance Rsh of the implanted layers is 1.5 kΩ/□. The technique for converting photoresist into nanocrystalline graphite is used to protect the SiC surface in the annealing after Ge+ ion implantations.     

物理学研究与微电子科学技术的发展

回顾了微电子学的诞生和微电子技术的发展历史，展望了微电子技术未来的发展趋势。在微电子技术延生和发展中具有一些里程碑式的发明，如晶体管、集成电路、集成电路平面工艺、MOS器件、微处理器、光刻技术、铜互连工艺的发明等，其中物理学研究和突破起子关键的基础作用。在社会需求、物理学研究和技术进步的推动下，微电子技术一直并将继续以特征尺寸缩小、集成度提高的模式，按摩尔定律预测的指数增长率发展。微电子技术的发展，不仅为物理学的研究提供了崭新的技术基础，而且为物理学研究展现了更为广阔的空间。但随着器件特征尺寸逐渐缩小并逼近期物理极限，微电子技术的发展将受到来自于材料、工艺和物理基础等方面的挑战，并呈现出多维发展的趋势，这些挑战涉及了微电子学与物理学的共同理论基础，需要二者互相锲合，期待新的突破。     

A novel 10-nm physical gate length double-gate junction field effect transisto

A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.     

A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

In this paper, a complementary metal-oxide semiconductor （CMOS）-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon （SGPS） trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.     

Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

Nitrogen plasma passivation(NPP) on(111) germanium(Ge) was studied in terms of the interface trap density,roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition(PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interfacial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness(EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.     

面向产业需求的21世纪微电子技术的发展(上)

微电子产业是国民经济与国防建设的战略性基础产业．对此，我国经历了发展时期的奋斗，现正处于微电子产业迅速崛起的前夕，预计经过10—15年左右时间的努力，将把我国建设成为微电子产业和科学技术的强国．文章着重介绍了21世纪微电子产业的发展需求，面向这个需求，讨论了21世纪微电子科学技术的主要发展方向．认为：一方面，特征尺寸将继续等比例缩小(scaling down)，包括新结构、新工艺、新材料的器件设计与制备技术以及光刻技术、互连技术将迅速发展；基于特征尺寸继续等比例缩小，系统芯片(SOC)将取代目前的集成电路(IC)最终成为主流产品；另一方面，纳电子学也将得到突破性进展，量子器件、分子电子器件等的相关研究日益活跃，期望最终达到可集成的目标；此外，微电子技术与其他领域相结合诞生出的新的技术增长点和新的学科——微机电系统(MEMS)技术等也将继续快速发展．文章阐述了相关发展方向存在的挑战和可能的解决方案，对可能进一步开展的具有重要学术意义和应用价值的研究工作进行了探讨．     

Theoretical and experimental analysis of the effects of the series resistance on luminous efficacy in GaN-based light emitting diodes

In this paper, a new equivalent circuit model of GaN-based light emitting diodes （LEDs） is established. The impact of the series resistance to luminous efficacy is simulated using the MATLAB software. GaN-based LEDs with different n- contact electrode materials （LEDs with Ni/Au and LEDs with Cr/Au） are fabricated. By comparing and analyzing the results of performances, we concluded that both the series resistance and the carrier loss could affect the luminous efficacy severely. LEDs with lower series resistance have higher luminous efficacy and its efficiency droop is alleviated simultaneously. To improve luminous efficacy, the fabrication process should be optimized for lower series resistance.     

微米尺度结构最大抗扭强度的在线测试和研究

提出了一种新型的测试结构，对面积为微米量级下键合的最大抗扭强度进行了测试.实验设计一系列的单晶硅悬臂梁结构测试键合面积在微米量级时的最大剪切力，键合面为常用的矩形其边长从6μm到120μm，并根据实际移动距离计算得出的最大剪切力.并实验实际得出最大剪切扭矩和相应的键合面积的曲线，以及最大扭转剪切破坏应力与悬臂梁加载距离的关系，并针对60μm×60μm的矩形键合结构进行了加载和位移的重复性实验测量，两次测量结果符合较好.微电子机械系统(microelectromechanical system, MEMS)器件的设计人员可以根据结论曲线，针对所需的抗扭强度设计相应的键合面积，为MEMS器件工艺的在线定量测试与设计提供参考. 关键词： 阳极键合 硅深刻蚀 键合强度 最大抗扭强度     

面向产业需求的21世纪微电子技术的发展(下)

在新器件制备工艺技术方面，超浅结工艺、沟道掺杂工程是器件进入亚100nm领域后需要采用的新工艺技术．     

Tradeoff between speed and static power dissipation of ultra-thin body SOI MOSFETs

The speed performance and static power dissipation of the ultra-thin-body （UTB） MOSFETs have been comprehensively investigated, with both DC and AC behaviours considered. Source/drain extension width （Lsp） and silicon film thickness （tsi） are two independent parameters that influence the speed and static power dissipation of UTB siliconon-insulator （SOI） MOSFETs respectively, which can result in great design flexibility. Based on the different effects of physical and geometric parameters on device characteristics, a method to alleviate the contradiction between power dissipated and speed of UTB SOI MOSFETs is proposed. The optimal design regions of tsi and Lsp for low operating power and high performance logic applications are given, which may shed light on the design of UTB SOI MOSFETs.