Effects of Ti addition on sol-gel derived InO and InZnO thin film transistors

In this study, we have newly developed titanium-indium oxide (TiInO) and titanium-indium zinc oxide (TiInZnO) thin films as the active channel layer in thin film transistors (TFTs) by the sol-gel process. The effects of adding Ti on TiInO and TiInZnO TFTs were investigated. The addition of Ti elements can suppress formation of oxygen vacancies because of the stronger oxidation tendency of Ti relative to that of Zn or In. TiInO and TiInZnO TFTs showed lower off currents and higher on/off current ratios than pure InO and InZnO TFTs. A TiInO TFT doped with 10.31 mol% Ti showed good performance with an on/off current ratio greater than 10⁷, and a field-effect mobility of 1.91 cm² V^?1 S^?1. A TiInZnO TFT doped with 2.92 mol % Ti showed an on/off current ratio greater than 10⁶, and a field-effect mobility of 0.45 cm² V^?1 S^?1.     

A study of electrical enhancement of polycrystalline MgZnO/ZnO bi-layer thin film transistors dependence on the thickness of ZnO layer

A polycrystalline MgZnO/ZnO bi-layer was deposited by using a RF co-magnetron sputtering method and the MgZnO/ZnO bi-layer TFTs were fabricated on the thermally oxidized silicon substrate. The performances with varying the thickness of ZnO layer were investigated. In this result, the MgZnO/ZnO bi-layer TFTs which the content of Mg is about 2.5 at % have shown the enhancement characteristics of high mobility (6.77–7.56 cm² V⁻¹ s⁻¹) and low sub-threshold swing (0.57–0.69 V decade⁻¹) compare of the ZnO single layer TFT (μ_FE = 5.38 cm² V⁻¹ s⁻¹; S.S. = 0.86 V decade⁻¹). Moreover, in the results of the positive bias stress, the ΔV_on shift (4.8 V) of MgZnO/ZnO bi-layer is the 2 V lower than ZnO single layer TFT (ΔV_on = 6.1 V). It reveals that the stability of the MgZnO/ZnO bi-layer TFT enhanced compared to that of the ZnO single layer TFT.     

Effect of antimony doping on the low‐temperature performance of solution‐processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution‐processed indium oxide (InO_x) thin film transistors (TFTs) were examined. The Sb‐doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high I_ON/OFF ratio of 4.6 cm²/V s, 0.29 V/decade, 1.9 V, and 3 × 10⁷, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InO_x TFTs. This improvement was attributed to the reduction of oxygen‐related defects and/or the existence of the lone‐pair s‐electron of Sb³⁺ in amorphous InSbO films. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Indium zinc oxide thin films deposited by sputtering at room temperature

The deposition of amorphous indium zinc oxide (IZO) thin films on glass substrates with n-type carrier concentrations between 10¹⁴ and 3 × 10²⁰ cm⁻³ by sputtering from single targets near room temperature was investigated as a function of power and process pressure. The resistivity of the films with In/Zn of ∼0.7 could be controlled between 5 × 10⁻³ and 10⁴ Ω cm by varying the power during deposition. The corresponding electron mobilities were 4-18 cm² V⁻¹ s⁻¹.The surface root-mean-square roughness was <1 nm under all conditions for film thicknesses of 200 nm. Thin film transistors with 1 μm gate length were fabricated on these IZO layers, showing enhancement mode operation with good pitch-off characteristics, threshold voltage 2.5 V and a maximum transconductance of 6 mS/mm. These films look promising for transparent thin film transistor applications.     

氧对IZO低压无结薄膜晶体管稳定性的影响

本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管, 并研究了氧分压对其稳定性的影响. 氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点, 然而氧化物沟道层易受氧、水分子等影响, 造成稳定性下降. 在室温下, 本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极, 分析了氧压对于氧化物无结薄膜晶体管稳定性的影响. 为使晶体管在低电压(<2 V)下工作, 达到低压驱动效果, 本文采用具有双电层效应和栅电容大的二氧化硅纳米颗粒膜作为栅介质; 通过电学性能测试, 制备的晶体管工作电压仅为1 V、 开关电流比大于10⁶、亚阈值斜率小于100 mV/decade以及场效 应迁移率大于20 cm²/V·s. 实验研究表明, 通氧制备的氧化铟锌薄膜的电阻率会上升, 导致晶体管的阈值电压向正向漂移, 最终使晶体管的工作模式由耗尽型转变为增强型. 关键词： 薄膜晶体管 无结 氧化铟锌 氧分子     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Nonvolatile unipolar resistive switching in ultrathin films of graphene and carbon nanotubes

We report unipolar resistive switching in ultrathin films of chemically produced graphene (reduced graphene oxide) and multiwalled carbon nanotubes. The two-terminal devices with yield >99% are made at room temperature by forming continuous films of graphene of thickness ∼20 nm on indium tin oxide coated glass electrode, followed by metal (Au or Al) deposition on the film. These memory devices are nonvolatile, rewritable with ON/OFF ratios up to ∼ 10⁵ and switching times up to 10 μs. The devices made of MWNT films are rewritable with ON/OFF ratios up to ∼400. The resistive switching mechanism is proposed to be nanogap formation and filamentary conduction paths.     

Highly stable amorphous indium‐zinc‐oxide thin‐film transistors with back‐channel wet‐etch process

The stabilities of amorphous indium‐zinc‐oxide (IZO) thin film transistors (TFTs) with back‐channel‐etch (BCE) structure are investigated. A molybdenum (Mo) source/drain electrode was deposited on an IZO layer and patterned by hydrogen peroxide (H₂O₂)‐based etchants. Then, after etching the Mo layer, SF₆ plasma with direct plasma mode was employed and optimized to improve the bias stress stability. Scanning electron microscopy and X‐ray photoelectron spectroscopic analysis revealed that the etching residues were removed efficiently by the plasma treatment. The modified BCE‐ TFTs showed only threshold voltage shifts of 0.25 V and –0.20 V under positive/negative bias thermal stress (P/NBTS, V_GS = ±30 V, V_DS = 0 V and T = 60 °C) after 12 hours, respectively. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

A p-channel SMC poly-Si thin film-transistor with a GOLDD structure

We have developed a silicide-mediated crystallization (SMC) polycrystalline silicon (poly-Si) thin film transistor (TFT) with a gate overlapped lightly doped drain (GOLDD) structure. Applying a GOLDD structure to the SMC poly-Si TFT, the off-state leakage current of coplanar TFT is reduced, while the reduction of the on-state current is relatively small. The p-channel poly-Si TFT with a GOLDD structure exhibited a field effect mobility of 50 cm²/V s and an off-state leakage current of 3.8×10⁻¹¹ A/μm at the drain voltage of −5 V and the gate voltage of 10 V.     

Low-voltage-drive and high output current ZnO thin-film transistors with sputtering SiO2 as gate insulator

Low-voltage-drive ZnO thin-film transistors (TFTs) with room-temperature radio frequency magnetron sputtering SiO₂ as the gate insulator were fabricated successfully on the glass substrate. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 4.2 V, a field effect mobility of 11.2 cm²/V s, an on/off ratio of 3.1 × 10⁶ and a subthreshold swing of 0.61 V/dec. The drain current can reach to 1 mA while the gate voltage is only of 12 V and drain voltage of 8 V. The C–V characteristics of a MOS capacitor with the structure of ITO/SiO₂/ZnO/Al was investigated. The carrier concentration N_D in the ZnO active layer was determined, the calculated N_D is 1.81 × 10¹⁶ cm⁻³, which is the typical value of undoped ZnO film used as the channel layer for ZnO-TFT devices. The experiment results show that SiO₂ film is a promising insulator for the low voltage and high drive capability oxide TFTs.     

Investigation of the electrical properties and stability of HfInZnO thin-film transistors

In this study, amorphous HfInZnO (a-HIZO) thin films and related thin-film transistors (TFTs) were fabricated using the RF-sputtering method. The effects of the sputtering power (50–200 W) on the structural, surface, electrical, and optical properties of the a-HIZO films and the performance and NBIS stability of the a-HIZO TFTs were investigated. The films’ N_e increased and resistivity decreased as the sputtering power increased. The 100 W deposited a-HIZO film exhibited good optical and electrical properties compared with other sputtering powers. Optimization of the 100 W deposited a-HIZO TFT demonstrated good device performance, including a desirable μ_FE of 19.5 cm²/Vs, low SS of 0.32 V/decade, low V_th of 0.8 V, and high I_on/I_off of 10⁷, respectively. The 100 W deposited a-HIZO TFT with Al₂O₃ PVL also exhibited the best stability, with small V_th shifts of -2.2 V during NBIS testing. These high-performance a-HIZO thin films and TFTs with Al₂O₃ PVL have practical applications in thin-film electronics.     

Enhanced contact properties of spray-coated AgNWs source and drain electrodes in oxide thin-film transistors

Facile patterning of electrodes is required for various electronic applications, particularly in solution-processed oxide thin-film transistors (TFTs). In this study, source and drain electrodes were prepared from silver nanowires (AgNWs) using spray-coating and hot press techniques. Although spray coating allowed production of AgNW patterns, which could function as electrodes in oxide TFT, the as-sprayed films did not provide a sufficient physical contact with oxide semiconductors and formed interspaces that impeded electron injection. At the same time, hot press technique produced denser AgNW networks that had a tight contact with the oxide semiconductors. As a result, hot-pressed films were considered as satisfactory source and drain electrodes for high-performance oxide TFTs, as they provided an easy electron injection. Finally, the prepared oxide TFTs with hot-pressed AgNW electrodes exhibited average field-effect mobility of 4.75 ± 1.5 cm²/V, significantly higher than that of the TFTs with as-sprayed AgNW electrodes (0.08 ± 0.05 cm²/V).     

The effect of annealing in forming gas on the a-IGZO thin film transistor performance and valence band cut-off of IGZO on SiNx

In this investigation, the carrier concentration gradient between channel and contact region is achieved to improve the Thin film Transistors (TFT) performance by employing annealing at 350 °C in forming gas (N₂ + 5% H₂). The contact region is covered with Mo metal and the channel region is only exposed to forming gas to facilitate the diffusion controlled reaction. The TFT using a-IGZO active layer is fabricated in ambient of Ar:O₂ in ratio 60:40 and the conductivity of the order of 10⁻³ S/cm is measured for as-deposited sample. The electrical conductivity of an annealed sample is of the order of 10² S/cm. The device performance is determined by measuring merit factors of TFT. The saturation mobility of magnitude 18.5 cm²V⁻¹ s⁻¹ has been determined for W/L (20/10) device at 15 V drain bias. The extrapolated field effect mobility for a device with channel width (W) 10 μm is 19.3 cm²V⁻¹ s⁻¹. The on/off current ratio is 10⁹ and threshold voltage is in the range between 2 and 3 V. The role of annealing on the electronic property of a-IGZO is carried out using X-ray photoelectron spectroscopy (XPS). The valance band cut-off has been approximately shifted to higher binding energy by 1 eV relative to as-deposited sample.     

微晶硅薄膜晶体管稳定性研究

对有源区处于结构过渡区的微晶硅底栅薄膜晶体管，测试其偏压衰退特性时，观察到一种“自恢复”的衰退现象.当栅和源漏同时施加10 V的偏压时，测试其源-漏电流随时间的变化，发现源-漏电流先衰减、而后又开始恢复上升的反常现象.而当采用栅压为10 V、源-漏之间施加零偏压的模式时，源-漏电流随时间呈先是几乎指数式下降、随之是衰退速度减缓的正常衰退趋势.就此现象进行了初步探讨. 关键词： 过渡区硅材料 微晶硅薄膜晶体管 稳定性 自恢复衰退     

Improved performance of InGaZnO thin-film transistors with Ta2O5/Al2O3 stack deposited using pulsed laser deposition

Ta₂O₅/Al₂O₃ stacked thin film was fabricated as the gate dielectric for low-voltage-driven amorphous indium–gallium–zinc-oxide (IGZO) thin film transistors (TFTs). The Ta₂O₅/Al₂O₃ stacked thin film exhibits a combination of the advantages of Al₂O₃ and Ta₂O₅. The IGZO TFT with Ta₂O₅/Al₂O₃ stack exhibits good performance with large saturation mobility of 26.66 cm² V⁻¹ s⁻¹, high on/off current ratio of 8 × 10⁷, and an ultra-small subthreshold swing (SS) of 78 mV/decade. Such small SS value is even comparable with that of submicrometer single-crystalline Si MOSFET.     

High mobility organic thin-film transistors on plastic substrate

We have fabricated organic thin-film transistors (OTFTs) based on di-n-decyldinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C₁₀-DNTT) on a polyimide gate dielectric coated on a polycarbonate substrate with a bottom-gate, top-contact configuration. Mobilities of the C₁₀-DNTT-based TFTs were as high as 2.4 cm² V^?1 s^?1, which are much better than those of the parent dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT)-based TFTs (mobility ～ 0.5 cm²/V) fabricated on the same substrate. Compared to the C₁₀-DNTT-TFTs on the conventional Si/SiO₂ substrate, the present mobility of C₁₀-DNTT-TFTs are somewhat reduced, which can be attributed to reduced crystallinity on the polyimide gate dielectric, although the crystalline phase on the polyimide is the same as on the Si/SiO₂ substrate.     

铟锌氧化物薄膜晶体管局域态分布的提取方法

本文针对铟锌氧化物薄膜晶体管(IZO TFT)的低频噪声特性与变频电容-电压特性展开试验研究,基于上述特性对有源层内局域态密度及其在禁带中的分布进行参数提取.首先,基于IZO TFT的亚阈区I-V特性提取器件表面势随栅源电压的变化关系.基于载流子数随机涨落模型,在考虑有源层内缺陷态俘获/释放载流子效应基础上,通过γ因子提取深能态陷阱的特征温度;基于沟道电流噪声功率谱密度及平带电压噪声功率谱密度的测量,提取IZO TFT有源层内局域态密度及其分布.试验结果表明,带尾态缺陷在禁带内随能量呈e指数变化趋势,其导带底密度N1TA约为3.42×10~(20)cm~(-3)·eV-,特征温度TTA约为135 K.随后,将C-V特性与线性区I-V特性相结合,对栅端寄生电阻、漏端寄生电阻、源端寄生电阻进行提取与分离.在考虑有源层内局域态所俘获电荷与自由载流子的情况下,基于变频C-V特性对IZO TFT有源层内局域态分布进行参数提取.试验结果表明,深能态与带尾态在禁带内随能量均呈e指数变化趋势,深能态在导带底密度NDA约为5.4×10~(15)cm~(-3)·eV~(-1),特征温度TDA约为711 K,而带尾态在导带底密度NTA约为1.99×10~(20)cm~(-3)·eV~(-1),特征温度TTA约为183 K.最后,对以上两种局域态提取方法进行对比与分析.     

The effect of post-metal annealing on the electrical performance and stability of two-step-annealed solution-processed In2O3 thin film transistors

In this work, solution-processed indium oxide (In₂O₃) thin film transistors (TFTs) were fabricated by a two-step annealing method. The influence of post-metal annealing (PMA) temperatures on the electrical performance and stability is studied. With the increase of PMA temperatures, the on-state current and off-state current (I_on/I_off) ratio is improved and the sub-threshold swing (SS) decreased. Moreover, the stability of In₂O₃ TFTs is also improved. In all, In₂O₃ TFT with post-metal annealing temperature of 350°С exhibits the best performance (a threshold voltage of 4.75 V, a mobility of 13.8 cm²/V, an I_on/I_off ratio of 1.8 × 10⁶, and a SS of 0.76 V/decade). Meanwhile, the stability under temperature stress (TBS) and positive bias stress (PBS) also show a good improvement. It shows that the PMA treatment can effectively suppress the interface trap and bulk trap and result in an obviously improvement of the In₂O₃ TFTs performance.