Extraction of density-of-states in amorphous InGaZnO thin-film transistors from temperature stress studies

The instability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with different active layer thicknesses under temperature stress has been investigated through using the density-of-states (DOS). Interestingly, the a-IGZO TFT with 22 nm active layer thickness showed a better stability than the others, which was observed from the decrease of interfacial and semiconductor bulk trap densities. The DOS was calculated based on the experimentally-obtained activation energy (E_A), which can explain the experimental observations. We developed the high-performance Al₂O₃ TFT with 22 nm IGZO channel layer (a high mobility of 7.4 cm²/V, a small threshold voltage of 2.8 V, a high I_on/I_off 1.8 × 10⁷, and a small SS of 0.16 V/dec), which can be used as driving devices in the next-generation flat panel displays.     

Investigation of the electrical properties and stability of HfInZnO thin-film transistors

In this study, amorphous HfInZnO (a-HIZO) thin films and related thin-film transistors (TFTs) were fabricated using the RF-sputtering method. The effects of the sputtering power (50–200 W) on the structural, surface, electrical, and optical properties of the a-HIZO films and the performance and NBIS stability of the a-HIZO TFTs were investigated. The films’ N_e increased and resistivity decreased as the sputtering power increased. The 100 W deposited a-HIZO film exhibited good optical and electrical properties compared with other sputtering powers. Optimization of the 100 W deposited a-HIZO TFT demonstrated good device performance, including a desirable μ_FE of 19.5 cm²/Vs, low SS of 0.32 V/decade, low V_th of 0.8 V, and high I_on/I_off of 10⁷, respectively. The 100 W deposited a-HIZO TFT with Al₂O₃ PVL also exhibited the best stability, with small V_th shifts of -2.2 V during NBIS testing. These high-performance a-HIZO thin films and TFTs with Al₂O₃ PVL have practical applications in thin-film electronics.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In-Ga-Zn-O as the n-channel active layer and SiO₂ as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO₂ with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm²/V s, the I_on/I_off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.     

Chemical bath deposition of CdS channel layer for fabrication of low temperature-processed thin-film-transistors

～66 nm thick CdS film with a hexagonal structure was uniformly generated via a low temperature-processed chemical bath deposition at 80 °C using a complexing agent of ethylenediaminetetraacetic acid and its crystal structure, surface morphology, optical transmittance, and Raman scattering property were measured. Grown CdS film was used as a channel layer for the fabrication of bottom-gate, top-contact thin-film-transistor (TFT). The TFT device with 60 °C-dried channel layer exhibited a poor electrical performance of on-to-off drain current ratio (I_on/I_off) of 5.1 × 10³ and saturated channel mobility (μ_sat) of 0.10 cm²/Vs. However, upon annealing at 350 °C, substantially improved electrical characteristics resulted, showing I_on/I_off of 5.9 × 10⁷ and μ_sat of 5.07 cm²/Vs. Furthermore, CdS channel layer was chemically deposited in an identical way on a transparent substrate of SiN_x/ITO/glass as part of transparent TFT fabrication, resulting in I_on/I_off of 5.8 × 10⁷ and μ_sat of 2.50 cm²/Vs.     

Effect of Ge doping on the electrical properties of amorphous Zn–Sn–O thin films

We report the effect of germanium doping on the active layer of amorphous Zinc–Tin-Oxide (a-ZTO) thin film transistor (TFT). Amorphous thin film samples were prepared by RF magnetron sputtering using single targets composed of Zn₂Ge_0.05Sn_0.95O₄ and Zn₂SnO₄ with variable oxygen contents in the sputtering gases. In comparison with undoped, Ge-doped a-ZTO films exhibited five order of magnitude lower carrier density with a significantly higher Hall-mobility, which might be due to suppressed oxygen vacancies in the a-ZTO lattice since the Ge substituent for the Sn site has relatively higher oxygen affinity. Thus, the bulk and interface trap densities of Ge-doped a-ZTO film were decreased one order of magnitude to 7.047 × 10¹⁸ eV⁻¹cm⁻³ and 3.52 × 10¹¹ eV⁻¹cm⁻², respectively. A bottom-gate TFT with the Ge-doped a-ZTO active layer showed considerably improved performance with a reduced SS, positively shifted V_th, and two orders of magnitude increased I_on/I_off ratio, attributable to the doped Ge ions.     

Improved performance of InGaZnO thin-film transistors with Ta2O5/Al2O3 stack deposited using pulsed laser deposition

Ta₂O₅/Al₂O₃ stacked thin film was fabricated as the gate dielectric for low-voltage-driven amorphous indium–gallium–zinc-oxide (IGZO) thin film transistors (TFTs). The Ta₂O₅/Al₂O₃ stacked thin film exhibits a combination of the advantages of Al₂O₃ and Ta₂O₅. The IGZO TFT with Ta₂O₅/Al₂O₃ stack exhibits good performance with large saturation mobility of 26.66 cm² V⁻¹ s⁻¹, high on/off current ratio of 8 × 10⁷, and an ultra-small subthreshold swing (SS) of 78 mV/decade. Such small SS value is even comparable with that of submicrometer single-crystalline Si MOSFET.     

Fabrication of thin-film transistor based on self-assembled single-walled carbon nanotube network

Thin-film transistor based on controllable electrostatic self-assembled monolayer single-wall carbon nanotubes (SWNTs) network has been fabricated by varying the density of nanotubes on the silicon substrate. The densities of SWNTs network have been investigated as a function of concentration and assembly time. It has been observed that the density of SWNTs network increases from 0.6 µm⁻² to 2.1 µm⁻², as the average on-state current (I_on) increases from 0.5 mA to 1.47 mA. The device has a current on/off ratio (I_on/I_off) of 1.3×10⁴ when I_on reaches to 1.34 mA.     

High-performance Zinc-Tin-Oxide thin film transistors based on environment friendly solution process

Zinc-Tin-Oxide (ZTO) thin films were fabricated using a simple and eco-friendly sol-gel method and their application in thin film transistors (TFTs) was investigated. Annealing temperature has a crucial influence on the structure and electrical properties of sol-gel ZTO thin films. The ZTO thin films annealed at 300–600?°C revealed smooth and uniform surfaces with amorphous state, in addition, a high optical transparency over 90% of the ZTO films in the visible range was obtained. The electrical performance of ZTO TFTs showed obvious dependence on annealing temperature. The ZTO TFTs annealed at 500?°C showed a high carrier mobility of 5.9?cm²/V, high on/off current ratio (I_on/off) of 10⁶-10⁷, and threshold voltage (V_th) of 1.03?V. To demonstrate the application of sol-gel ZTO films in low-power display fields, we also fabricated ZTO TFTs with a solution-processed high-permittivity (high-k) ZrTiO_x dielectric layer. The ZTO/ZrTiO_x TFTs showed high mobility of 17.9?cm²/V and I_on/off of 10⁵-10⁶?at a low operation voltage of 3?V, indicating that Indium-free ZTO thin films would be potential candidates for low cost, high performance oxide TFT devices.     

Thin film transistors based on TiO2 fabricated by using radio-frequency magnetron sputtering

This study demonstrates that nanocrystalline TiO₂ thin films were deposited on ITO/glass substrate by radio-frequency magnetron sputtering. Field-emission scanning electron microscope (FE-SEM) and atomic force microscopic (AFM) images showed the morphology of TiO₂ channel layer with grain size and root-mean-square (RMS) roughness of 15 and 5.39 nm, respectively. TiO₂ thin-film transistors (TFTs) with sputter-SiO₂ gate dielectric layer were also fabricated. It was found that the devices exhibited enhancement mode characteristics with the threshold voltage of 7.5 V. With 8-μm gate length, it was also found that the I_on/off ratio and off-state current were around 1.45×10² and 10 nA, respectively.     

A study of electrical enhancement of polycrystalline MgZnO/ZnO bi-layer thin film transistors dependence on the thickness of ZnO layer

A polycrystalline MgZnO/ZnO bi-layer was deposited by using a RF co-magnetron sputtering method and the MgZnO/ZnO bi-layer TFTs were fabricated on the thermally oxidized silicon substrate. The performances with varying the thickness of ZnO layer were investigated. In this result, the MgZnO/ZnO bi-layer TFTs which the content of Mg is about 2.5 at % have shown the enhancement characteristics of high mobility (6.77–7.56 cm² V⁻¹ s⁻¹) and low sub-threshold swing (0.57–0.69 V decade⁻¹) compare of the ZnO single layer TFT (μ_FE = 5.38 cm² V⁻¹ s⁻¹; S.S. = 0.86 V decade⁻¹). Moreover, in the results of the positive bias stress, the ΔV_on shift (4.8 V) of MgZnO/ZnO bi-layer is the 2 V lower than ZnO single layer TFT (ΔV_on = 6.1 V). It reveals that the stability of the MgZnO/ZnO bi-layer TFT enhanced compared to that of the ZnO single layer TFT.     

Enhancement of electrical stability of a-IGZO TFTs by improving the surface morphology and packing density of active channel

a-IGZO films were deposited on Si substrates by d.c sputtering technique with various working power densities (p_d) in the range of 0.74–2.22 W/cm². The correlation between material properties and their effects on electrical stability of a-IGZO thin-film transistor (TFTs) was studied as a function of p_d. At a p_d of 1.72 W/cm² a-IGZO film had smoothest surface roughness (0.309 nm) with In-rich and Ga-poor cation compositions as a channel. This structurally ordered TFTs exhibited a high field effect mobility of 9.14 cm²/Vs, a sub-threshold swing (S.S.) of 0.566 V/dec, and an on–off ratio of 10⁷. Additionally, the V_th shift in hysteresis loop is almost eliminated. It was shown that the densification of the a-IGZO film resulted in the reduction of its interface trap density (1.83 × 10¹² cm^?2), which contributes for the improvement in the electrical and thermal stability.     

In2O3 透明薄膜晶体管的制备及其电学性能的研究

采用磁控溅射方法在玻璃衬底上生长了In₂O₃晶体薄膜.该薄膜具有(111)晶面择优取向,晶粒尺寸达到33 nm.利用光刻工艺制作了以In₂O₃晶体薄膜为沟道层的底栅式薄膜晶体管.In₂O₃薄膜晶体管具有良好的栅压调制特性,场效应迁移率达到6.3 cm²/(V·s),开关电流比为3×10³,阈值电压为-0.9 V.结果表明,In相似文献   

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

Improvement of electrical characteristics of InGaZnO thin film transistors by using HMDSO/O2 plasma deposited SiOCH buffer layer

In this work, we present the performance improved InGaZnO thin film transistors by inserting low temperature processed 10 nm thick SiOCH buffer layers between SiN_x insulator and InGaZnO channel layer. The influences of oxygen flow rate during the deposition of SiOCH buffer layer have been intensively investigated. Basing on the analysis of hall effect measurement and Fourier transform infrared spectrum, the SiOCH buffer layer can effectively increase the carrier concentration of the channel layer by the hydrogen doping due to re-sputtering and diffusion effect. The InGaZnO thin film transistor with buffer layer exhibits an enhanced performance with mobility of 13.09 cm²/vs, threshold voltage of −0.55 V and I_on/I_off over 10⁶.     

Memory properties of a Ge nanocrystal MOS device fabricated by pulsed laser deposition

The charge–storage properties of Ge nanocrystal (Nc) memory devices with MOS structure have been studied. The Ge nanocrystals (Ncs) were prepared on a p-Si (100) matrix by means of pulsed laser deposition (PLD) combined with rapid annealing in the presence of Ar gas. The device is characteristic of better switching characteristics (the I _on/I _off>10⁵), low leakage current, which was attributed to the effect of Coulomb blockade preventing injection. A significant threshold-voltage shift of 0.85 V was observed when an operating voltage of 5 V was implemented on the device. The kind of hysteresis behavior in the double sweep suggests that the device has a good electrostatic control over the Ge Nc channel.     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Utilization of surface plasmon resonance of Au/Pt nanoparticles for highly photosensitive ZnO nanorods network based plasmon field effect transistor

Hydrothermally processed highly photosensitive ZnO nanorods based plasmon field effect transistors (PFETs) have been demonstrated utilizing the surface plasmon resonance coupling of Au and Pt nanoparticles at Au/Pt and ZnO interface. A significantly enhanced photocurrent was observed due to the plasmonic effect of the metal nanoparticles (NPs). The Pt coated PFETs showed I_on/I_off ratio more than 3 × 10⁴ under the dark condition, with field-effect mobility of 26 cm² V⁻¹ s⁻¹ and threshold voltage of −2.7 V. Moreover, under the illumination of UV light (λ = 350 nm) the PFET revealed photocurrent gain of 10⁵ under off-state (−5 V) of operation. Additionally, the electrical performance of PFETs was investigated in detail on the basis of charge transfer at metal/ZnO interface. The ZnO nanorods growth temperature was preserved at 110 °C which allowed a low temperature, economical and simple method to develop highly photosensitive ZnO nanorods network based PFETs for large scale production.     

High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Low voltage organic field effect transistors with a poly(hexylthiophene)–ZnO nanoparticles composite as channel material

We report on solution processable organic field effect transistors prepared using a poly(3‐hexylthiophene)–ZnO nanoparticles composite as channel semiconductor material and cross‐linked polyvinyl alcohol as gate insulator. Our transistors show a field effect mobility of 0.35 ± 0.06 cm²/V s, threshold voltage of –1.30 ± 0.11 V, and I_on/I_off ratio of (1.0 ± 0.1) × 10³. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)