双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

薄膜热处理对ZnO薄膜晶体管性能的提高

制备了两种以SiO2为绝缘层的底栅ZnO薄膜晶体管,分别以未退火和退火处理的ZnO薄膜作为有源层.与未退火处理的ZnO薄膜晶体管相比,退火处理的ZnO薄膜晶体管的饱和迁移率由2.3 cm2/(V·s)增大至3.12 cm2/(V·s),阈值电压由20.8V减小至9.9V,亚阈值摆幅由2.6 V/dec减小至1.9 V/...     

High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Ultra‐high long‐term stability of oxide‐TTFTs under current stress

In this letter the stability of transparent thin‐film transistors (TTFTs) based on the ZnO–SnO₂ (ZTO) material system is investigated. Bottom‐gate devices have been subject to electrical stress via a gate–source bias of 10 V and a drain‐source bias of 10 V leading to a drain–source current of 188 µA. In optimized TTFTs with a composition of [Zn]:[Sn] = 36:64 the relative change of the saturated field effect mobility was less than 1% and the threshold voltage shift was about 320 mV after 1000 hours of operation. This extraordinary stability of ZTO TTFTs underlines their suitability as drivers in active matrix OLED displays. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Electrical in‐situ characterisation of interface stabilised organic thin‐film transistors

We report on the electrical in‐situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom‐gate/bottom‐contact (coplanar) configuration are electrically characterised in‐situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO₂ with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor param‐ eters is studied on a bi‐layer dielectric of a 150 nm of SiO₂ and 20 nm of poly((±)endo,exo‐bicyclo[2.2.1]hept‐5‐ene‐2,3‐dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO₂ dielectric. The thin layer of PNDPE, which is an intrinsically photo‐patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Identification of grain boundaries as degradation site in n‐channel organic field‐effect transistors determined via conductive atomic force microscopy

One important figure of merit for the commercial usability of organic transistors (OFETs) is their electrical stability. With the aim of identifying the microscopic location of degradation sites within a transistor channel, we have investigated the bias stress stability of OFETs by electrical measurements as well as by conductive atomic force microscopy. Air‐stable n‐channel FETs based on a N,N′‐bis(2‐ethylhexyl)‐1,7(1,6)‐dicyano‐perylene[3,4:9,10]bis (dicarboximide) were fabricated to understand the relation between the thin‐film morphology, the substrate temperature during the vacuum de position with the aim to fabricate transistors with a mobility not dominated by interface traps. The devices showed a maximum carrier mobility of (0.12 ± 0.01) cm²/V s and an on/off ratio up to 10⁷. The electrical performance as well as the bias stress behavior of the semiconductor thin‐films is significantly influenced by grain boundaries. For example, the grain boundary resistance was found to increase upon electrical stress by more than 150% (from 2 ± 0.2 GΩ to 5 ± 1.5 GΩ), while the resistance within the grains remains unchanged. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Enhanced performances of ZnO-TFT by improving surface properties of channel layer

Top-contact thin film transistors with ZnO as the channel layer and thermally grown SiO₂ as the gate dielectric were fabricated by using rf sputtering. The performances of ZnO-TFTs with different thicknesses of the active layer were investigated and the optimized condition was obtained. With the active layer thickness from 25 to 70 nm, the leakage current of devices increased from 10⁻¹⁰ to 10⁻⁸ A, and the on/off ratio decreased from 1.2×10⁷ to 2×10⁴. Atomic force microscope research indicated that with the thickness increased, the surface morphology of the active layer improved noticeably at first and then deteriorated. The 25-nm-thick ZnO TFT had the best surface morphology, and showed the best performance with a field effect mobility of 5.1 cm²/V S, on/off ratio of 1.2×10⁷ and threshold voltage of 20 V. This indicates that the surface properties of the channel layer have crucial affects on the performances of ZnO-TFTs.     

低温透明非晶IGZO薄膜晶体管的光照稳定性

采用室温射频磁控溅射非晶铟镓锌氧化合物(a-IGZO), 在相对低的温度(<200 ℃)下成功制备底栅a-IGZO 薄膜晶体管器件, 其场效应迁移率10 cm^-2·V^-1·s^-1, 开关比大于10⁷, 亚阈值摆幅 SS为0.4 V/dec, 阈值电压为3.6 V. 栅电压正向和负向扫描未发现电滞现象. 白光发光二极管光照对器件的输出特性基本没有影响, 表明制备的器件可用于透明显示器件. 研究了器件的光照稳定性, 光照10000 s后器件阈值电压负向偏移约0.8 V, 这种漂移是由于界面电荷束缚所致. 关键词： 非晶铟镓锌氧化合物 薄膜晶体管 光照稳定性 电滞现象     

Interface engineering with an MOCVD grown ZnO interface passivation layer for ZrO2-GaAs metal-oxide-semiconductor devices

This work deals with the fabrication of a GaAs metal-oxide-semiconductor device with an unpinned interface environment. An ultrathin (∼2 nm) interface passivation layer (IPL) of ZnO on GaAs was grown by metal organic chemical vapor deposition to control the interface trap densities and to prevent the Fermi level pinning before high-k deposition. X-ray photoelectron spectroscopy and high resolution transmission electron microscopy results show that an ultra thin layer of ZnO IPL can effectively suppress the oxides formation and minimize the Fermi level pinning at the interface between the GaAs and ZrO₂. By incorporating ZnO IPL, GaAs MOS devices with improved capacitance-voltage and reduced gate leakage current were achieved. The charge trapping behavior of the ZrO₂/ZnO gate stack under constant voltage stressing exhibits an improved interface quality and high dielectric reliability.     

Highly stable amorphous indium‐zinc‐oxide thin‐film transistors with back‐channel wet‐etch process

The stabilities of amorphous indium‐zinc‐oxide (IZO) thin film transistors (TFTs) with back‐channel‐etch (BCE) structure are investigated. A molybdenum (Mo) source/drain electrode was deposited on an IZO layer and patterned by hydrogen peroxide (H₂O₂)‐based etchants. Then, after etching the Mo layer, SF₆ plasma with direct plasma mode was employed and optimized to improve the bias stress stability. Scanning electron microscopy and X‐ray photoelectron spectroscopic analysis revealed that the etching residues were removed efficiently by the plasma treatment. The modified BCE‐ TFTs showed only threshold voltage shifts of 0.25 V and –0.20 V under positive/negative bias thermal stress (P/NBTS, V_GS = ±30 V, V_DS = 0 V and T = 60 °C) after 12 hours, respectively. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

氧对IZO低压无结薄膜晶体管稳定性的影响

本文在室温下制备了无结结构的低压氧化铟锌薄膜晶体管, 并研究了氧分压对其稳定性的影响. 氧化铟锌无结薄膜晶体管具有迁移率高、结构新颖等优点, 然而氧化物沟道层易受氧、水分子等影响, 造成稳定性下降. 在室温下, 本文通过改变高纯氧流量制备氧化铟锌透明导电薄膜作为沟道层、源漏电极, 分析了氧压对于氧化物无结薄膜晶体管稳定性的影响. 为使晶体管在低电压(<2 V)下工作, 达到低压驱动效果, 本文采用具有双电层效应和栅电容大的二氧化硅纳米颗粒膜作为栅介质; 通过电学性能测试, 制备的晶体管工作电压仅为1 V、 开关电流比大于10⁶、亚阈值斜率小于100 mV/decade以及场效 应迁移率大于20 cm²/V·s. 实验研究表明, 通氧制备的氧化铟锌薄膜的电阻率会上升, 导致晶体管的阈值电压向正向漂移, 最终使晶体管的工作模式由耗尽型转变为增强型. 关键词： 薄膜晶体管 无结 氧化铟锌 氧分子     

Effect of channel thickness on electrical performance of amorphous IGZO thin-film transistor with atomic layer deposited alumina oxide dielectric

We have investigated the electrical performance of amorphous indium–gallium–zinc oxide (α-IGZO) thin-film transistors with various channel thicknesses. It is observed that when the α-IGZO thickness increases, the threshold voltage decreases as reported at other researches. The intrinsic field-effect mobility as high as 11.1 cm²/Vs and sub threshold slope as low as ∼0.2 V/decade are independent on the thickness of α-IGZO channel, which indicate the excellent interface between α-IGZO and atomic layer deposited Al₂O₃ dielectric even for the case with α-IGZO thickness as thin as 10 nm. However, the source and drain series resistances increased with increasing of α-IGZO channel thickness, which results in the apparent field-effect mobility decreasing. The threshold voltage shift (ΔV_th) under negative bias stress (NBS) and negative bias illumination stress (NBIS) were investigated, also. The hump-effect in the sub threshold region under NBS and threshold voltage shift to negative position under NBIS were enhanced with decreasing of α-IGZO channel thickness, owing to the enhancement of vertical electrical field in channel.     

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride (HfSiON) on ultrathin SiO₂ buffer layer. The gate dielectric with 10? (1?= 0.1 nm) equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant (k=14) and low gate-leakage current (I_g=1.9×10^-3A/cm² @V_g=V_fb-1V for EOT of 10?). TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.     

A study of electrical enhancement of polycrystalline MgZnO/ZnO bi-layer thin film transistors dependence on the thickness of ZnO layer

A polycrystalline MgZnO/ZnO bi-layer was deposited by using a RF co-magnetron sputtering method and the MgZnO/ZnO bi-layer TFTs were fabricated on the thermally oxidized silicon substrate. The performances with varying the thickness of ZnO layer were investigated. In this result, the MgZnO/ZnO bi-layer TFTs which the content of Mg is about 2.5 at % have shown the enhancement characteristics of high mobility (6.77–7.56 cm² V⁻¹ s⁻¹) and low sub-threshold swing (0.57–0.69 V decade⁻¹) compare of the ZnO single layer TFT (μ_FE = 5.38 cm² V⁻¹ s⁻¹; S.S. = 0.86 V decade⁻¹). Moreover, in the results of the positive bias stress, the ΔV_on shift (4.8 V) of MgZnO/ZnO bi-layer is the 2 V lower than ZnO single layer TFT (ΔV_on = 6.1 V). It reveals that the stability of the MgZnO/ZnO bi-layer TFT enhanced compared to that of the ZnO single layer TFT.     

Effect of antimony doping on the low‐temperature performance of solution‐processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution‐processed indium oxide (InO_x) thin film transistors (TFTs) were examined. The Sb‐doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high I_ON/OFF ratio of 4.6 cm²/V s, 0.29 V/decade, 1.9 V, and 3 × 10⁷, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InO_x TFTs. This improvement was attributed to the reduction of oxygen‐related defects and/or the existence of the lone‐pair s‐electron of Sb³⁺ in amorphous InSbO films. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Influence of polymer dielectric surface energy on thin‐film transistor performance of solution‐processed triethylsilylethynyl anthradithiophene (TES‐ADT)

This study investigates the correlation between surface energy of polymer dielectrics and the film morphology, microstructure, and thin‐film transistor performance of solution‐processed 5,11‐bis(triethylsilylethynyl) anthradithiophene (TES‐ADT) films. The low surface energy polyimide (PI) dielectric induced large grains with strong X‐ray reflections for spin‐cast TES‐ADT films in comparison to high surface en‐ ergy poly(4‐vinyl phenol) (PVP) dielectric. Furthermore, thin‐film transistors based on spin‐cast TES‐ADT films on PI dielectric exhibited enhanced electrical performance, small hysteresis, and high stability under bias stress with carrier mobility as high as 0.43 cm²/Vs and a current on/off ratio of 10⁷. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

Si-doped zinc oxide(SZO) thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated.Moreover,the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure.The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm,and the optical band gap of the SZO film gradually increases with increasing Si content.The Si-doping can effectively suppress the grain growth of ZnO,revealed by atomic force microscope analysis.Compared with that of the undoped ZnO TFT,the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10~(-12) A,and thus the on/off current ratio is increased by more than two orders of magnitude.In summary,the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 10~6 and superior stability under gate-bias and drain-bias stress.     

Effect of crystallinity of ZnO buffer layer on the properties of epitaxial (ZnO:Al)/(ZnO:Ga) bi-layer films deposited on c-sapphire substrate

Bi-layer ZnO films with 2 wt.% Al (AZO; ZnO:Al) and 4 wt.% Ga-doped (GZO; ZnO:Ga) were deposited on the ZnO buffered and annealed ZnO buffered c(0 0 0 1)-sapphire(Al₂O₃) substrates respectively by Pulsed Laser Deposition (PLD). The effect of crystallinity of ZnO buffer layer on the crystallinity and electrical properties of the AZO/GZO bi-layer thin films was investigated. It was seen that the crystallinity of ZnO buffer layer had a great influence on the orientation and defect density of AZO/GZO bi-layer thin films from X-ray Diffraction (XRD) peaks and High Resolution Transmission Electron Microscopy (HRTEM) images. In a word, it was found in the films that more preferred c-axis orientation texture and reduction of the defects such as stacking faults and dislocations, with increasing of the crystallinity of ZnO buffer layer.     

Effect of Al doping on microstructure and optical band gap of ZnO thin film synthesized by successive ion layer adsorption and reaction

Thin films of pure and aluminum-doped zinc oxide (AZO) were deposited on glass substrates from ammonium zincate bath following a chemical dipping technique called successive ion layer adsorption and reaction (SILAR). Characterization techniques such as X-ray diffraction (XRD), scanning electron microscopy (SEM) and energy-dispersive X-rays (EDX) were used to investigate the effect of Al doping on the microstructure of AZO films. Particle size analysis using X-ray line broadening shows marginally increasing trend with increasing Al impurity. The average particle size for pure ZnO is 22.75 nm. It increases to 24.26 nm for 1% AZO film and 25.13 nm for 2% AZO film. Incorporation of Al was confirmed from elemental analysis using EDX. SEM micrograph shows that pure ZnO particles are spherical shaped. However, AZO films show particles with off-spherical shape with compact interconnected grains. The value of band gap for pure ZnO is 3.229 eV and it increases to 3.29 eV for 1% AZO indicating a blue-shift for 1% AZO film. However, for 2% AZO film, a decrease in band gap compared to pure ZnO is observed indicating a red-shift of fundamental absorption edge. Electrical resistance shows an initial decrease with increasing Al content. With further enhancement of Al incorporation, the resistance increases.