共查询到19条相似文献,搜索用时 984 毫秒
1.
2.
探索了ITO/PMMA/Al器件的阻变机理及其SPICE电路仿真, 通过优化聚甲基丙烯酸甲酯(PMMA)层退火温度, 器件可实现连续擦-读-写-读操作. 基于不同退火温度PMMA薄膜的表面形貌研究, 构建了单层有机阻变器件的非线性电荷漂移模型, 以及描述该模型掺杂区界面移动的状态方程, 并通过反馈控制积分器建立了SPICE仿真电路. 最后, 代入器件实际测量参数, 得到与器件实际结果基本一致的电流-电压模拟曲线. 结果验证了单层有机器件的阻变机理, 说明该非线性电荷漂移模型的SPICE仿真在有机阻变器件仿真中同样适用.
关键词:
有机阻变存储器
非线性电荷漂移
SPICE仿真 相似文献
3.
低温电力电子技术的发展日益得到重视,主要是由于功率器件(如功率MOSFET和IGBT等)在低温下表现出更好的性能,如更低的通态阻抗,更高的开关频率等.为了实验测试和充分利用功率器件在低温下的这些性能,急需寻找或设计可以在低温下稳定可靠工作的功率器件驱动电路.我们在对目前商业化的驱动芯片进行分析的基础上,从中挑选了三种在低温下进行实验,对其输出波形随温度的变化进行研究,首次发现了可以在-196℃(77K)稳定工作的驱动芯片,其驱动性能基本能够满足低温下驱动功率器件的要求,为功率器件低温特性测试及低温功率变换电路的设计奠定了坚实的基础. 相似文献
4.
采用溶胶-凝胶法制备了系列多晶CMR材料La2/3(Cao 60Bao.40)1/3Mn1-xVXO3,(x:0%、1%、5%、7%、10%、15%、20%).在零场下、77~350 K温度范围内测量了其电阻率随温度的变化关系,测量了该温度范围内0.1 T磁场下磁化强度随温度的变化关系.采用小极化子绝热跃迁模型P=aTexp(E/kT)对样品的电导特性进行拟合研究.结果发现,高温区电阻率随温度的变化很好地满足小极化子绝热跃迁模型;同时,采用单磁子散射模型对样品低温区的电输运曲线进行拟合,结果发现所有样品低温区的p~T关系同样都很好地满足单磁子散射公式P=po AT2严.由拟合结果分析了样品高温区的输运行为主要来源于小极化子的影响,而低温区电导特性主要来源于单磁子散射. 相似文献
5.
介绍了低温低噪声放大器使用的HEMT(高迁移率晶体管)器件噪声模型的建立,对HEMT用S参数和噪声参数讲行仿直,获取适合的模型.给出了实例,放大器在低温10K工作,增益≥30dB,噪声温度≤4K. 相似文献
6.
7.
磁开关是重复频率脉冲功率系统可选的工作性能优越的开关器件之一。目前磁开关的仿真模型是基于伏秒积分的宏观特性建立起来的纯电路模型,未考虑磁芯饱和过程中磁芯特性的变化,仿真难以准确预测磁开关负载上的预脉冲,波形的前沿误差也较大。测试获得了快脉冲激励下的铁基纳米晶磁芯磁滞回线和初始磁化曲线,利用磁芯磁滞回线的关键参数,提取了脉冲激励下的磁芯J-A参数,用于定义多物理场中磁开关模型的磁芯特性。针对磁开关脉冲压缩电路,利用多物理场仿真软件COMSOL建立了磁脉冲压缩系统电路与磁开关电磁场的场路耦合仿真模型,计算磁脉冲压缩电路的输出波形,与实验结果对比,预脉冲幅值误差为2%,峰值误差为2%,前沿误差为5%,证明了建立的场路耦合仿真模型的有效性和准确性。 相似文献
8.
本文给出了准确描述硅雪崩渡越时间二极管工作特性的大信号仿真模型,研究了影响硅雪崩越时间(IMPATY,Impact Avalanche Transit Time)二极管工作状态的离化率和饱和漂移速度,考虑Si-IMPATT二极管热限制的条件下,计算了二极管的最大工作电流.通过大信号仿真分析,我们得到如下结果:(1)随着温度的降低,二极管输出功率提高;(2)随着温度的降低,二极管工作频率向高端偏移,本文还建立了液氮制冷环境下IMPATT振荡器的测试系统,与常温工作相比,77K低温环境下IMPATT二极管的输出功率提高了47.8%,频率也向高端偏移了6.3%,实验结果与仿真预测一致. 相似文献
9.
10.
《强激光与粒子束》2021,(10)
利用Sentaurus-TCAD建立了CMOS与非门电路的二维电热模型,仿真研究了在电磁脉冲注入下,CMOS与非门电路产生的扰乱和损伤效应及其机理。结果表明,在EMP注入下,电路输出电压、内部的峰值温度呈周期性的"下降-上升",当注入功率较大时,EMP撤销后输出电压停留在异常值,PMOS源极电流增加,温度不断上升,最终烧毁在PMOS源极,这是因为器件内部产生了闩锁效应。随着脉宽的增加,损伤功率阈值减小而损伤能量阈值增大,通过数据拟合得到脉宽与损伤功率阈值和损伤能量阈值的关系。该结果可对EMP损伤效应进行评估并对器件级EMP抗毁伤加固设计具有指导作用。 相似文献
11.
基于建立的不同工艺尺寸的CMOS器件模型,利用TCAD器件模拟的方法,针对不同工艺CMOS器件,开展了不同工艺尺寸CMOS器件单粒子闩锁效应(SEL)的研究。研究表明,器件工艺尺寸越大,SEL效应越敏感。结合单粒子闩锁效应触发机制,提出了保护带、保护环两种器件级抗SEL加固设计方法,并通过TCAD仿真和重离子试验验证防护效果,得出最优的加固防护设计。结果表明,90nm和0.13μm CMOS器件尽量选用保护带抗SEL结构,0.18μm或更大工艺尺寸CMOS器件建议选取保护环抗SEL结构。 相似文献
12.
The factors affecting the feasibility of cryogenically cooled CMOS are reviewed. This approach becomes more attractive as CMOS feature sizes shrink below 250?nm where chip performance is limited by interconnect characteristics. The impact of interconnects is demonstrated using a methodology for estimating interconnect-limited CMOS performance. The cryogenic behavior of normal and superconducting interconnects is reviewed. Cooling the best normal interconnect metals such as Al or Cu to 77?K can produce 9×lower resistivity. High-temperature superconductors can produce lower resistance at GHz clock frequencies, but would be difficult to produce on low dielectric substrates compatible with silicon technology. Performance doubling has been demonstrated for CMOS circuits operating at liquid nitrogen temperature. Comparable performance improvements may be expected down to below 100?nm if process technology is adjusted appropriately. In addition, dramatic increases in DRAM storage times result from exponential decreases in subthreshold leakage currents. Circuit reliability should increase correspondingly, apart from hot-carrier induced degradation. Thermally efficient packages and refrigerators are required for cryogenic CMOS. Microchannel heat exchangers can produce thermally efficient cryogenic packages. However, thermodynamic limits to refrigerator performance may make operation at higher cryogenic temperatures more attractive. 相似文献
13.
Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process 总被引:2,自引:0,他引:2 下载免费PDF全文
N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process
have been fabricated and characterized. For the devices with channel length
of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for
n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate
n-MOSFET was 150 times less than that of a conventional planar n-MOSFET.
These results demonstrate that groove-gate MOSFETs have excellent
capabilities in suppressing short-channel effects. It is worth emphasizing
that our groove-gate MOSFET devices are fabricated by using a simple process
flow, with the potential of fabricating devices in the sub-100nm range. 相似文献
14.
The experimental results of the cryogenic temperature characteristics on 0.18-μm silicon-on-insulator(SOI) metaloxide-silicon(MOS) field-effect-transistors(FETs) were presented in detail. The current and capacitance characteristics for different operating conditions ranging from 300 K to 10 K were discussed. SOI MOSFETs at cryogenic temperature exhibit improved performance, as expected. Nevertheless, operation at cryogenic temperature also demonstrates abnormal behaviors, such as the impurity freeze-out and series resistance effects. In this paper, the critical parameters of the devices were extracted with a specific method from 300 K to 10 K. Accordingly, some temperature-dependent-parameter models were created to improve fitting precision at cryogenic temperature. 相似文献
15.
16.
17.
18.
19.
Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution 下载免费PDF全文
The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result,the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated,and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures. 相似文献