考虑通孔效应和边缘传热效应的纳米级互连线温度分布模型

提出了同时考虑通孔效应和边缘传热效应的互连线温度分布模型,获得了适用于单层互连线和多层互连线温度分布的解析模型,并基于65 nm互补金属氧化物半导体（CMOS）工艺参数计算了不同长度单层互连线和多层互连线的温度分布.对于单层互连线,考虑通孔效应后中低层互连线的温升非常低,而全局互连线几乎不受通孔效应的影响,温升仍然很高.对于多层互连线,最上层互连线的温升最高,温升和互连介质层厚度近似成正比,而且互连介质材料热导率越低,温升越高.所提出的互连线温度分布模型,能应用于纳米级CMOS计算机辅助设计. 关键词： 通孔效应 边缘传热效应 纳米级互连线 温度分布模型     

CMOS电路低温特性及其仿真

本文采用0.25微米工艺制备了CMOS器件和电路,通过对300K、77K和4K温度下器件和电路特性的测量,研究了工作温度降低对CMOS电路特性的影响.通过讨论MOSFET器件和互连线主要特性参数随温度的变化情况,修改了常温CMOS BSIM3模型以及互连线参数,建立了77K、4K温度下的低温电路仿真模型.利用上述新建立的低温电路仿真模型对CMOS电路进行仿真,并将仿真结果与实际测量结果比较,获得了比较一致的结果.研究表明在4K温度下CMOS电路的工作性能大约有50%到60%的改善.     

基于双电源电压和双阈值电压的全局互连性能优化

基于双电源电压和双阈值电压技术,提出了一种优化全局互连性能的新方法.文中首先定义了一个包含互连延时、带宽和功耗等因素的品质因子用以描述全局互连特性,然后在给定延时牺牲的前提下,通过最大化品质因子求得优化的双电压数值用以节省功耗.仿真结果显示,在65 nm工艺下,针对5%,10%和20%的允许牺牲延时,所提方法相较于单电压方法可分别获得27.8%,40.3%和56.9%的功耗节省.同时发现,随着工艺进步,功耗节省更加明显.该方法可用于高性能全局互连的优化和设计. 关键词： 全局互连 双电源电压 双阈值电压 功耗     

An RLC interconnect analyzable crosstalk model considering self-heating effect

According to the thermal profile of actual multilevel interconnects, in this paper we propose a temperature distribution model of multilevel interconnects and derive an analytical crosstalk model for the distributed resistance-inductance-capacitance (RLC) interconnect considering effect of thermal profile. According to the 65-nm complementary metal-oxide semiconductor (CMOS) process, we compare the proposed RLC analytical crosstalk model with the Hspice simulation results for different interconnect coupling conditions and the absolute error is within 6.5%. The computed results of the proposed analytical crosstalk model show that RCL crosstalk decreases with the increase of current density and increases with the increase of insulator thickness. This analytical crosstalk model can be applied to the electronic design automation (EDA) and the design optimization for nanometer CMOS integrated circuits.     

一种基于纳米级CMOS工艺的互连线串扰RLC解析模型

基于纳米级CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了分布式RLC耦合互连解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下提出了受扰线远端的数值表达式. 基于90和65 nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在4%内,能应用于纳米级片上系统（SOC）的电子设计自动化（EDA）设计和集成电路优化设计. 关键词： 纳米级CMOS 互连串扰 分布式 RLC解析模型')" href="#">RLC解析模型     

一种基于延时和带宽约束的纳米级互连线优化模型

基于RLC互连线延时模型,通过缓冲器插入和改变互连线宽及线间距,提出了一种基于延时和带宽约束的互连功耗-缓冲器面积的乘积优化模型.基于90 nm,65 nm和45 nm CMOS工艺验证了互连线优化模型,在牺牲1/3和1/2的带宽的前提下,平均能够节省46%和61%的互连功耗,以及65%和83%的缓冲器面积,能应用于纳米级SOC的计算机辅助设计. 关键词： 纳米互连功耗 缓冲器面积 延时 带宽     

一种考虑温度的分布式互连线功耗模型

基于集总式电阻-电容树形功耗模型,考虑了非均匀温度分布对互连线电阻的影响,提出了一种新的分布式互连线动态功耗解析模型,解决了集总式模型不能表征非均匀温度变化带来的电阻变化的问题,并计算了一次非理想的激励冲激下整个互连模型消耗的总能量.基于所提出的分布式互连线功耗模型,计算了纳米级互补金属氧化物半导体（CMOS）工艺典型长度互连线的Elmore延时和功耗,发现非均匀温度分布对互连功耗的影响随着互连线长度的增加而增加,单位长度功耗随着CMOS工艺特征尺寸的变化而基本不变.文中所提出的功耗模型可以用来精确估算互 关键词： 互连线 温度梯度 动态功耗模型 纳米级互补金属氧化物半导体     

Systematic study on the mechanical and electric behaviors of the nonbuckling interconnect design of stretchable electronics

Recently, we developed a nonbuckling interconnect design that provides an effective approach to simultaneously achieving high elastic stretchability, easiness for encapsulation, and high electric performance for stretchable electronics. This paper aims to systematically study its mechanical and electric behaviors, including comparisons of the nonbuckling and buckling interconnect designs on stretchability, effects of the thickness on electric performance, and modeling and experimental investigations on the finite deformation mechanics. It is found that the results on stretchability depend on the layouts. Long straight segments and small arc radii for nonbuckling interconnects yield an enhancement of stretchability, which is much better than that of buckling designs. On the other hand, shorter straight segments or thicker interconnects are better to lower the resistances of interconnects.Therefore, optimization of the designs needs to balance the requirements of both the mechanical and electric performances. The finite deformation of interconnects during stretching is analyzed. The established analytic model is well validated by both the finite element modeling and experimental investigations. This work is key for providing the design guidelines for nonbucklingbased stretchable electronics.     

一种非均匀线型的互连线能量分布模型

基于互连线信号传输微分方程,推导非均匀互连线的电压和电流分布表达式,根据实际情况,考虑非理性激励提出包括前端驱动和后端负载的二端口非均匀互连电路各部分能量分布表达式.基于65 nm CMOS工艺参数,对方法进行计算仿真验证,计算结果与Hspice仿真结果比较误差小于5%,具有很高的精度.该方法适用于高性能全局互连的前端优化设计分析.     

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits.Based on the RLC interconnect delay model,by wire sizing,wire spacing and adopting low-swing interconnect technology,this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously.The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor(CMOS) interconnect parameters.The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process.The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.     

CMOS monolithic optoelectronic integrated circuit for on-chip optical interconnection

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated using standard 0.35-μm CMOS technology. This OEIC monolithically integrates light emitting diode (LED), silicon dioxide waveguide, photodetector and receiver circuit on a single silicon chip. The silicon LED operates in reverse breakdown mode and can emit light at 8.5 V. The output optical power is 31.2 nW under 9.8 V reverse bias. The measured spectrum of LED showed two peaks at 760 nm and 810 nm, respectively. The waveguide is composed of silicon dioxide/metal multiple layers. The responsivity of the n-well/p-substrate diode photodetector is 0.42 A/W and the dark current is 7.8 pA. The LED-emitted light transmits through the waveguide and can be detected by the photodetector. Experimental results show that on-chip optical interconnects are achieved by standard CMOS technology successfully.     

A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS

Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.     

High-power diode-pumped cryogenically cooled Yb:CaF₂ laser with extremely low quantum defect

High-power diode-pumped laser operation at 992-993 nm under a pumping wavelength of 981 of 986 nm is demonstrated with Yb:CaF? operating at cryogenic temperature (77 K), leading to extremely low quantum defects of 1.2% and 0.7%, respectively. An average output power of 33 W has been produced with an optical efficiency of 35%. This represents, to the best of our knowledge, the best laser performance ever obtained at such low quantum defects on intense laser lines.     

Simultaneous dual mode add/drop multiplexers for optical interconnects buses

For the potential realization of optical interconnect scheme based on modal diversity, we propose and analyze efficient mode add drop multiplexers (MADM). Each of the two types of MADM proposed here enables a simultaneous two channels (modes) add/drop to/from a multimode bus. The simultaneous operation is of importance in reducing the device footprint within the expected ultra-dense interconnects schemes. We developed analytical design rules for the adiabatic devices and verified by simulation that an implementation based on Silicon over Insulator waveguides, is exhibiting low loss and low channels crosstalk (below −22 dB).     

High-efficiency,high-speed VCSELs for optical interconnects

High-efficiency, high-speed, tapered-oxide-apertured vertical-cavity surface-emitting lasers (VCSELs) emitting at 980 nm have been demonstrated. By carefully engineering the tapered oxide aperture, the mode volume can be greatly reduced without adding much optical scattering loss for the device sizes of interest. Consequently, these devices can achieve higher bandwidth at lower current and power dissipation. In addition, the parasitics are reduced by implementing deep oxidation layers and an improved p-doping scheme in the top mirror. Our devices show modulation bandwidth exceeding 20 GHz, a record for 980 nm VCSELs. Moreover, 35 Gb/s operation has been achieved at only 10 mW power dissipation. This corresponds to a data-rate/power-dissipation ratio of 3.5 Gbps/mW. Most importantly, our device structure is compatible with existing manufacturing processes and can be easily manufactured in large volume making them attractive for optical interconnects.     

Fabrication and characterization of hollow metal waveguides for optical interconnect applications

As data rates continue to increase in high-performance computer systems and networks, it is becoming more difficult for copper-based interconnects to keep pace. An alternative approach to meet these requirements is to move to optical-based interconnect technologies which offer a number of advantages over the legacy copper-based solutions. In order to meet the stringent requirements of high performance and low cost, manufacturable waveguide technologies must be developed. Past solutions have often employed polymer waveguide technologies, which can be expensive and limited by modal dispersion. In the present work, hollow metal waveguides (HMWGs) are investigated as a potential alternative. These waveguides demonstrate very low optical losses of <0.05 dB/cm and the capability to transmit at extremely high data rates. The fabrication, modeling, characterization of the HMWGs are discussed to enable photonic interconnect solutions for future generations of computer and server products.     

A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65~nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.     

Laser-plasma extreme ultraviolet source at 6.7?nm using a rotating cryogenic Xe target

A laser-plasma source comprising a rotating cryogenic solid-state Xe target has been studied for use in extreme ultraviolet lithography (EUVL) systems equipped with La/B₄C mirrors. The laser-to-EUV power conversion efficiency (CE) of the cryogenic Xe target was improved to achieve a maximum CE of 0.15?% at 6.7?nm with 0.6?% bandwidth. We successfully demonstrated the continuous generation of EUV light with an average power of 80?mW at 6.7?nm with 0.6?% bandwidth using a Nd:YAG slab laser at a repetition rate of 320?Hz and an average power of 100?W. Scaling-up of the laser-plasma source for use as a future EUVL source is also discussed.     

石墨烯沟道全自旋逻辑器件开关特性

由于石墨烯的电导率相比典型的金属材料更大,自旋弛豫时间更长,自旋轨道相互作用更弱,从而在相同的注入电流情况下,自旋电流在石墨烯材料中的耗散作用更弱.基于自旋传输和磁化动力学耦合模型,研究了石墨烯沟道全自旋逻辑器件的开关特性.结果显示,在相同的电源电压下和器件尺寸下,石墨烯沟道材料的全自旋逻辑器件磁矩翻转时间比Cu沟道更短,流入输出纳磁体的自旋电流更大.同时,长度越短、宽度越窄的沟道其开关时间更短,功耗更小.在满足磁体磁矩翻转的临界开关电流的情况下,石墨烯沟道的可靠工作长度也显著大于Cu沟道.所以石墨烯材料是相比于金属材料更理想的沟道材料.另外,通过合理选择沟道尺寸,能进一步降低器件开关时间和功耗.上述结论为全自旋逻辑器件的优化设计与应用提供了理论参考.     

Realization of KaptonTM based optical interconnect by KMnO4 wet etching

In the paper, based on KMnO₄ wet-etching technology PDMS (polydimethylsiloxane) based flexible optical interconnect packaged with Kapton^TM (Dupont) foils was successfully realized through a stable and effective bonding technology. The optical and mechanical properties of the PDMS waveguide layer remained unchanged before and after packaging with KMnO₄ etched Kapton foils. The mechanical stability limit of the tested optical interconnects is determined only by the intrinsic mechanical stability of the used PDMS materials. The optical loss at 850 nm is <0.05 dB/cm even after temperature treatments up to lead-free soldering temperatures of 260°C. In addition, the main mechanism of forming a good bonding between PDMS and Kapton foil was identified and analyzed as well.