高温超导限流器终端绝缘材料低温绝缘特性研究

基于高温超导限流器终端的电场分布特点,开展了G10环氧在液氮中的击穿特性研究、G10环氧在低温氮气和液氮中的沿面闪络特性研究,以及液氮和低温氮气的击穿特性研究。实验结果表明,击穿电压受施加电压类型、电极形状和电极间隙长度等因素的影响。利用Weibull分布得到了50%击穿电压和电极间隙的关系。实验结果可作为高温超导限流器终端设计的参考和依据。     

电荷失配对SiC半超结垂直双扩散金属氧化物半导体场效应管击穿电压的影响

Si C半超结垂直双扩散金属氧化物半导体场效应管(VDMOSFET)相对于常规VDMOSFET在相同导通电阻下具有更大击穿电压.在N型外延层上进行离子注入形成半超结结构中的P柱是制造Si C半超结VDMOSFET的关键工艺.本文通过二维数值仿真研究了离子注入导致的电荷失配对4H-Si C超结和半超结VDMOSFET击穿电压的影响,在电荷失配程度为30%时出现半超结VDMOSFET的最大击穿电压.在本文的器件参数下,P柱浓度偏差导致击穿电压降低15%时,半超结VDMOSFET柱区浓度偏差范围相对于超结VDMOSFET可提高69.5%,这意味着半超结VDMOSFET对柱区离子注入的控制要求更低,工艺制造难度更低.     

场板结终端对金刚石SBD内部电场分布及击穿特性的影响

建立了场板结终端对金刚石肖特基势垒二极管(SBD)的数值模拟模型,采用Silvaco软件中的器件仿真工具ATLAS模拟了场板长度L、绝缘层厚度TOX、衬底掺杂浓度NB、场板结构形状对器件内部电场分布以及击穿电压的影响,并对结果进行了物理分析和解释。结果表明:当TOX=0.4μm、NB=1015cm-3、L在0~0.2μm范围内时,击穿电压随着L的增加而增加;L0.2μm后,击穿电压开始下降。当L=0.2μm、NB=1015cm-3、TOX在0.1~0.4μm范围内时,击穿电压随着TOX的增加而增加;TOX0.4μm后,击穿电压开始下降。当L=0.2μm、TOX=0.4μm、NB=1015cm-3时,器件的击穿电压达到最大的1 873 k V。与普通场板结构相比,采用台阶场板可以更加有效地提高器件的击穿电压。     

薄栅氧化层经时击穿的参数表征研究

在恒压应力条件下测试了薄栅氧化层的击穿特性,研究了TDDB的击穿机理,讨论了栅氧化层面积对击穿特性的影响.对击穿电荷Q_BD进行了实验测试和分析,结果表明：击穿电荷Q_BD不是常数,它依赖栅氧化层面积和栅电压.对相关系数进行了拟合,给出了Q_BD的解析表达式. 关键词：     

In_(0.53)Ga_(0.47)As/InP雪崩光电二极管响应及电学特性

通过分子束外延生长和开管式Zn扩散方法,制备了低暗电流、宽响应范围的In_(0.53)Ga_(0.47)As/InP雪崩光电二极管.在0.95倍雪崩击穿电压下,器件暗电流小于10nA;-5V偏压下电容密度低至1.43×10~(-8) F/cm~2.在1 310nm红外光照及30V反向偏置电压下,雪崩光电二极管器件的响应范围为50nW~20mW,响应度达到1.13A/W.得到了电荷层掺杂浓度、倍增区厚度结构参数与击穿电压和贯穿电压的关系:随着电荷层电荷密度的增加,器件贯穿电压线性增加,而击穿电压线性降低;电荷层电荷面密度为4.8×10~(12)cm~(-2)时,随着倍增层厚度的增加,贯穿电压线性增加,击穿电压增加.通过对器件结构优化,雪崩光电二极管探测器实现25V的贯穿电压和57V的击穿电压,且具有低暗电流和宽响应范围等特性.     

结终端采用JTE保护技术的4H-SiC PiN二极管模拟和研制

利用二维器件模拟软件ISE-TCAD 10.0,对结终端采用结扩展保护技术的4H-SiC PiN二极管平面器件进行反向耐压特性的模拟,并获得许多有价值的模拟数据.依据所得的模拟数据进行此种二极管器件的研制.实验测试表明,此二极管的模拟优化数据与实验测试的结果一致性较好,4H-SiC PiN二极管所测得到的反向电压达1600 V,该反向耐压数值达到理想平面结的击穿耐压90%以上.     

背栅效应对SOI横向高压器件击穿特性的影响

提出一种SOI基背栅体内场降低BG REBULF(back-gate reduced BULk field)耐压技术. 其机理是背栅电压诱生界面电荷，调制有源区电场分布，降低体内漏端电场，提高体内源端电场，从而突破习用结构的纵向耐压限制，提高器件的击穿电压. 借助二维数值仿真，分析背栅效应对厚膜高压SOI LDMOS (>600V) 击穿特性的影响，在背栅电压为330V时，实现器件击穿电压1020V，较习用结构提高47.83%. 该技术的提出，为600V以上级SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路. 关键词： SOI 背栅 体内场降低 LDMOS     

基于silvaco-TCAD的In0.53Ga0.47As/InP红外探测器的仿真

采用silvaco-TCAD研究In0.53Ga0.47As/InP SAGCM-APD光电探测器,对探测器的结构参数对器件的电场分布、击穿电压和贯穿电压的影响进行仿真分析。研究表明电荷层对器件内部电场起到更好的调节作用,但过高的电荷层面密度会导致APD探测器的击穿电压与贯穿电压之差减小。倍增层厚度的增加使击穿电压先减小后增高,贯穿电压线性增加,同时耗尽层宽度变大,使器件电容减小。当倍增区厚度1 μm、偏压为-5 V时,器件电容密度达到了4.5×10-17 F/μm。反向偏置电压为30 V时,APD探测器在1.31 μm和1.55 μm波长下的响应度分别达到1 A/W和1.1 A/W     

不同电流下气体开关电极烧蚀特性实验研究

在不同短路电流条件下,进行了不锈钢(1Cr18Ni9Ti)电极气体火花开关连续多次自击穿放电实验,通过测量电极质量损失、表面粗糙度和自击穿电压的变化,研究电极烧蚀特性及其对自击穿性能的影响。实验结果表明:随着放电电流峰值和周期增大,电极材料烧损速率与电容电荷量呈线性增加,而电极表面烧蚀粗糙度与电流峰值呈线性增大,自击穿电压变化达到峰值和稳定区的放电次数减少,但稳定阶段的自击穿电压值及其相对标准偏差同时减少,五种放电电流情况下,自击穿电压概率密度分布均遵循高斯函数。     

SiC光导开关衬底与电极界面场强仿真与优化设计

研究电极结构、SiC与电极连接结构对界面场强的影响,通过电极边缘以及SiC晶体结构的优化降低界面处的电场增强,并通过高压试验测试优化电极结构的击穿电压。结果表明,优化电极倒角以及SiC晶体与电极的界面下埋可有效降低电场增强,在电极为圆倒角及界面使用焊料连接的结构下,使用介质环的器件在电压22 kV时击穿。     

Simulation study of a mixed terminal structure for 4H-SiC merged PiN/Schottky diode

In this paper, a mixed terminal structure for the 4H-SiC merged PiN/Schottky diode (MPS) is investigated, which is a combination of a field plate, a junction termination extension and floating limiting rings. Optimization is performed on the terminal structure by using the ISE-TCAD. Further analysis shows that this structure can greatly reduce the sensitivity of the breakdown voltage to the doping concentration and can effectively suppress the effect of the interface charge compared with the structure of the junction termination extension. At the same time, the 4H-SiC MPS with this termination structure can reach a high and stable breakdown voltage.     

Research on high-voltage 4H-SiC P-i-N diode with planar edge junction termination techniques

The planar edge termination techniques of junction termination extension (JTE) and offset field plates and field-limiting rings for the 4H-SiC P-i-N diode were investigated and optimized by using a two-dimensional device simulator ISE-TCAD10.0. By experimental verification, a good consistency between simulation and experiment can be observed. The results show that the reverse breakdown voltage for the 4H-SiC P-i-N diode with optimized JTE edge termination can accomplish near ideal breakdown voltage and much lower leakage current. The breakdown voltage can be near 1650 V, which achieves more than 90 percent of ideal parallel plane junction breakdown voltage and the leakage current density can be near 3 × 10-5 A/cm2.     

Experimental and numerical analyses of high voltage 4H-SiC junction barrier Schottky rectifiers with linearly graded field limiting ring

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky(JBS) rectifiers with a linearly graded field limiting ring(LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2(about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.     

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-$K$/low-$K$ compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-$K$ and low-$K$ layers due to the different dielectric constants of high-$K$ and low-$K$ dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p-n junction interface is suppressed due to the effects of the high-$K$ dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance ($R_{\rm on, sp}$) of 2.07 m$\Omega\cdot$cm$^{2}$ and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm$^{2}$, and a low turn-on voltage of 0.6 V.     

150?快速热氮化SiO2膜的击穿特性

对具有器件质量的150?厚SiO₂膜经传统的长时间热氮化和高温快速热氮化后,研究了其击穿特性及其在高场强下的耐久力。研究结果表明,氮化后击穿场强的分布变窄,对栅电极面积的依赖性减弱,最大击穿场强略微下降。热氮化对高电场下SiO₂/Si界面稳定性和决定于时间的介质击穿均有改善。这种改善既取决于所加栅电压的极性,又强烈依赖于氮化工艺条件。根据电流传输机构,本文提出一种考虑了电荷积累、陷阱密度及其重心位置的击穿模型。 关键词：     

Modeling of 4H--SiC multi-floating-junction Schottky barrier diode

This paper develops a new and easy to implement analytical model for the specific on-resistance and electric field distribution along the critical path for 4H-SiC multi-floating junction Schottky barrier diode. Considering the charge compensation effects by the multilayer of buried opposite doped regions, it improves the breakdown voltage a lot in comparison with conventional one with the same on-resistance. The forward resistance of the floating junction Schottky barrier diode consists of several components and the electric field can be understood with superposition concept, both are consistent with MEDICI simulation results. Moreover, device parameters are optimized and the analyses show that in comparison with one layer floating junction, multilayer of floating junction layer is an effective way to increase the device performance when specific resistance and the breakdown voltage are traded off. The results show that the specific resistance increases 3.2 mΩ·cm 2 and breakdown voltage increases 422 V with an additional floating junction for the given structure.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.