套刻偏差对4H-SiC 浮动结结势垒肖特基二极管的影响研究

4H-SiC浮动结结势垒肖特基二极管与常规结势垒肖特基二极管相比在 相同的导通电阻条件下具有更高的击穿电压. 由p⁺埋层形成的浮动结与主结p⁺区 之间的套刻对准是实现该结构的一项关键技术. 二维模拟软件ISE的模拟结果表明, 套刻偏差的存在会明显影响器件的击穿特性, 随着偏差的增大击穿电压减小. 尽管主结和埋层的交错结构与对准结构具有相似的击穿特性, 但是当正向电压大于2 V后, 交错结构的串联电阻更大.     

Study and optimal simulation of 4H-SiC floating junction Schottky barrier diodes’ structures and electric properties

This paper stuides the structures of 4H-SiC floating junction Schottky barrier diodes. Some structure parameters of devices are optimized with commercial simulator based on forward and reverse electrical characteristics. Compared with conventional power Schottky barrier diodes, the devices are featured by highly doped drift region and embedded floating junction layers, which can ensure high breakdown voltage while keeping lower specific on-state resistance, and solve the contradiction between forward voltage drop and breakdown voltage. The simulation results show that with optimized structure parameter, the breakdown voltage can reach 4.36 kV and the specific on-resistance is 5.8 mΩ·cm2 when the Baliga figure of merit value of 13.1 GW/cm2 is achieved.     

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-$K$/low-$K$ compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-$K$ and low-$K$ layers due to the different dielectric constants of high-$K$ and low-$K$ dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p-n junction interface is suppressed due to the effects of the high-$K$ dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance ($R_{\rm on, sp}$) of 2.07 m$\Omega\cdot$cm$^{2}$ and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm$^{2}$, and a low turn-on voltage of 0.6 V.     

Hybrid-anode structure designed for a high-performance quasi-vertical GaN Schottky barrier diode

A quasi-vertical GaN Schottky barrier diode with a hybrid anode structure is proposed to trade off the on-resistance and the breakdown voltage. By inserting a SiN dielectric between the anode metal with a relatively small length, it suppresses the electric field crowding effect without presenting an obvious effect on the forward characteristics. The enhanced breakdown voltage is ascribed to the charge-coupling effect between the insulation dielectric layer and GaN. On the other hand, the current density is decreased beneath the dielectric layer with the increasing length of the SiN, resulting in a high on-resistance. Furthermore, the introduction of the field plate on the side wall forms an metal-oxide-semiconductor (MOS) channel and decreases the series resistance, but also shows an obvious electric field crowding effect at the bottom of the mesa due to the quasi-vertical structure.     

具有L型源极场板的双槽绝缘体上硅高压器件新结构

为了提高小尺寸绝缘体上硅(SOI)器件的击穿电压,同时降低器件比导通电阻,提出了一种具有L型源极场板的双槽SOI高压器件新结构.该结构具有如下特征:首先,采用了槽栅结构,使电流纵向传导面积加宽,降低了器件的比导通电阻;其次,在漂移区引入了Si O2槽型介质层,该介质层的高电场使器件的击穿电压显著提高;第三,在槽型介质层中引入了L型源极场板,该场板调制了漂移区电场,使优化漂移区掺杂浓度大幅增加,降低了器件的比导通电阻.二维数值仿真结果表明:与传统SOI结构相比,在相同器件尺寸时,新结构的击穿电压提高了151%,比导通电阻降低了20%;在相同击穿电压时,比导通电阻降低了80%.与相同器件尺寸的双槽SOI结构相比,新结构保持了双槽SOI结构的高击穿电压特性,同时,比导通电阻降低了26%.     

Study of a double epi-layers SiC junction barrier Schottky rectifiers embedded P layer in the drift region

<正>This paper proposes a double epi-layers 4H—SiC junction barrier Schottky rectifier(JBSR) with embedded P layer (EPL) in the drift region.The structure is characterized by the P-type layer formed in the n-type drift layer by epitaxial overgrowth process.The electric field and potential distribution are changed due to the buried P-layer,resulting in a high breakdown voltage(BV) and low specific on-resistance(R_(on,sp)).The influences of device parameters,such as the depth of the embedded P+ regions,the space between them and the doping concentration of the drift region,etc.,on BV and R_(on,sp) are investigated by simulations,which provides a particularly useful guideline for the optimal design of the device.The results indicate that BV is increased by 48.5%and Baliga's figure of merit(BFOM) is increased by 67.9%compared to a conventional 4H-SiC JBSR.     

Design of vertical diamond Schottky barrier diode with junction terminal extension structure by using the n-Ga2O3/p-diamond heterojunction

A novel junction terminal extension structure is proposed for vertical diamond Schottky barrier diodes (SBDs) by using an n-Ga₂O₃/p-diamond heterojunction. The depletion region of the heterojunction suppresses part of the forward current conduction path, which slightly increases the on-resistance. On the other hand, the reverse breakdown voltage is enhanced obviously because of attenuated electric field crowding. By optimizing the doping concentration, length, and depth of n-Ga₂O₃, the trade-off between on-resistance and breakdown voltage with a high Baliga figure of merit (FOM) value is realized through Silvaco technology computer-aided design simulation. In addition, the effect of the work functions of the Schottky electrodes is evaluated. The results are beneficial to realizing a high-performance vertical diamond SBD.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

Edge termination study and fabrication of a 4Hben SiC junction barrier Schottky diode

The 4H-SiC junction barrier Schottky (JBS) diodes terminated by field guard rings and offset field plate are designed, fabricated and characterized. It is shown experimentally that a 3-μm P-type implantation window spacing gives an optimum trade-off between forward drop voltage and leakage current density for these diodes, yielding a specific on-resistance of 8.3 mΩ·cm². A JBS diode with a turn-on voltage of 0.65 V and a reverse current density less than 1 A/cm² under 500 V is fabricated, and the reverse recovery time is tested to be 80 ns, and the peak reverse current is 28.1 mA. Temperature-dependent characteristics are also studied in a temperature range of 75 ℃-200 ℃. The diode shows a stable Schottky barrier height of up to 200 ℃ and a stable operation under a continuous forward current of 100 A/cm².     

场板结终端对金刚石SBD内部电场分布及击穿特性的影响

建立了场板结终端对金刚石肖特基势垒二极管(SBD)的数值模拟模型,采用Silvaco软件中的器件仿真工具ATLAS模拟了场板长度L、绝缘层厚度TOX、衬底掺杂浓度NB、场板结构形状对器件内部电场分布以及击穿电压的影响,并对结果进行了物理分析和解释。结果表明:当TOX=0.4μm、NB=1015cm-3、L在0~0.2μm范围内时,击穿电压随着L的增加而增加;L0.2μm后,击穿电压开始下降。当L=0.2μm、NB=1015cm-3、TOX在0.1~0.4μm范围内时,击穿电压随着TOX的增加而增加;TOX0.4μm后,击穿电压开始下降。当L=0.2μm、TOX=0.4μm、NB=1015cm-3时,器件的击穿电压达到最大的1 873 k V。与普通场板结构相比,采用台阶场板可以更加有效地提高器件的击穿电压。     

Trapezoid mesa trench metal-oxide semiconductor barrier Schottky rectifier: an improved Schottky rectifier with better reverse characteristics

An improved structure of Schottky rectifier,called a trapezoid mesa trench metal-oxide semiconductor (MOS) barrier Schottky rectifier (TM-TMBS),is proposed and studied by two-dimensional numerical simulations.Both forward and especially better reverse I-V characteristics,including lower leakage current and higher breakdown voltage,are demonstrated by comparing our proposed TM-TMBS with a regular trench MOS barrier Schottky rectifier (TMBS) as well as a conventional planar Schottky barrier diode rectifier.Optimized device parameters corresponding to the requirement for high breakdown voltage are given.With optimized parameters,TM-TMBS attains a breakdown voltage of 186 V,which is 6.3% larger than that of the optimized TMBS,and a leakage current of 4.3×10 6 A/cm 2,which is 26% smaller than that of the optimized TMBS.The relationship between optimized breakdown voltage and some device parameters is studied.Explanations and design rules are given according to this relationship.     

具有半绝缘多晶硅完全三维超结横向功率器件

为了突破传统LDMOS (lateral double-diffused MOSFET)器件击穿电压与比导通电阻的硅极限的2.5 次方关系, 降低LDMOS器件的功率损耗, 提高功率集成电路的功率驱动能力, 提出了一种具有半绝缘多晶硅SIPOS (semi-insulating poly silicon)覆盖的完全3 D-RESURF (three-dimensional reduced surface field)新型Super Junction-LDMOS结构(SIPOS SJ-LDMOS). 这种结构利用SIPOS的电场调制作用使SJ-LDMOS的表面电场分布均匀, 将器件单位长度的耐压量提高到19.4 V/μupm; 覆盖于漂移区表面的SIPOS使SJ-LDMOS沿三维方向均受到电场调制, 实现了LDMOS的完全3 D-RESURF效应, 使更高浓度的漂移区完全耗尽而达到高的击穿电压; 当器件开态工作时, 覆盖于薄场氧化层表面的SIPOS的电场作用使SJ-LDMOS的漂移区表面形成多数载流子积累, 器件比导通电阻降低. 利用器件仿真软件ISE分析获得, 当SIPOS SJ-LDMOS的击穿电压为388 V时, 比导通电阻为20.87 mΩ·cm², 相同结构参数条件下, N-buffer SJ-LDMOS的击穿电压为287 V, 比导通电阻为31.14 mΩ·cm²; 一般SJ-LDMOS 的击穿电压仅为180 V, 比导通电阻为71.82 mΩ·cm².     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

Study of 4H-SiC junction barrier Schottky diode using field guard ring termination

This paper reports that the 4H-SiC Schottky barrier diode, PiN diode and junction barrier Schottky diode terminated by field guard rings are designed, fabricated and characterised. The measurements for forward and reverse characteristics have been done, and by comparison with each other, it shows that junction barrier Schottky diode has a lower reverse current density than that of the Schottky barrier diode and a higher forward drop than that of the PiN diode. High-temperature annealing is presented in this paper as well to figure out an optimised processing. The barrier height of 0.79 eV is formed with Ti in this work, the forward drop for the Schottky diode is 2.1 V, with an ideality factor of 3.2, and junction barrier Schottky diode with blocking voltage higher than 400 V was achieved by using field guard ring termination.     

Study and modeling of the transport mechanism in a semi insulating GaAs Schottky diode

The current through a metal–semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode: diffusion of carriers from the semiconductor into the metal, thermionic emission–diffusion (TED) of carriers across the Schottky barrier and quantum–mechanical tunneling through the barrier. The insulating layer converts the MS device in an MIS device and has a strong influence on its current–voltage (I–V) and the parameters of a Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behavior of Schottky diodes with and without an interfacial insulator layer. These include the particular distribution of interface states, the series resistance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase of the process of thermionic electrons and holes, which will in turn the IV characteristic of the diode, and an overflow maximum value [NT = 3 × 10²⁰] is obtained. The I–V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.     

具有P型覆盖层新型超级结横向双扩散功率器件

为了设计功率集成电路所需要的低功耗横向双扩散金属氧化物半导体器件(lateral double-diffused MOSFET), 在已有的N型缓冲层超级结LDMOS(N-buffered-SJ-LDMOS)结构基础上, 提出了一种具有P型覆盖层新型超级结LDMOS结构(P-covered-SJ-LDMOS). 这种结构不但能够消除传统的N沟道SJ-LDMOS由于P型衬底产生的衬底辅助耗尽问题, 使得超级结层的N区和P区的电荷完全补偿, 而且还能利用覆盖层的电荷补偿作用, 提高N型缓冲层浓度, 从而降低了器件的比导通电阻. 利用三维仿真软件ISE分析表明, 在漂移区长度均为10 μm的情况下, P-covered-SJ-LDMOS的比导通电阻较一般SJ-LDMOS结构降低了59%左右, 较文献提出的N型缓冲层 SJ-LDMOS(N-buffered-SJ-LDMOS)结构降低了43%左右.     

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

双面阶梯埋氧层部分SOI高压器件新结构

提出了双面阶梯埋氧层部分绝缘硅(silicon on insulator,SIO)高压器件新结构. 双面阶梯埋氧层的附加电场对表面电场的调制作用使表面电场达到近似理想的均匀分布, 耗尽层通过源极下硅窗口进一步向硅衬底扩展, 使埋氧层中纵向电场高达常规SOI结构的两倍, 且缓解了常规SOI结构的自热效应. 建立了漂移区电场的二维解析模型, 获得了器件结构参数间的优化关系. 结果表明, 在导通电阻相近的情况下, 双面阶梯埋氧层部分SOI结构击穿电压较常规SOI器件提高58％, 温度降低10—30K. 关键词： 双面阶梯 埋氧层 调制 自热效应     

New GaN Schottky barrier diode employing a trench on AlGaN/GaN heterostructure

A new GaN Schottky barrier diode employing a trench structure, which is proposed and fabricated, successfully decreases a forward voltage drop without sacrificing any other electric characteristics. The trench is located in the middle of Schottky contact during a mesa etch. The Schottky metal of Pt/Mo/Ti/Au is e-gun evaporated on the 300 nm-deep trench as well as the surface of the proposed GaN Schottky barrier diode. The trench forms the vertical Au Schottky contact and lateral Pt Schottky contact due to the evaporation sequence of Schottky metal. The forward voltage drops of the proposed diode and conventional one are 0.73 V and 1.25 V respectively because the metal work function (5.15 eV) of the vertical Au Schottky contact is considerably less than that of the lateral Pt Schottky contact (5.65 eV). The proposed diode exhibits the low on-resistance of 1.58 mΩ cm² while the conventional one exhibits 8.20 mΩ cm² due to the decrease of a forward voltage drop.     

Comparison of electrical characteristic between AlN/GaN and AlGaN/GaN heterostructure Schottky diodes

Ni/Au Schottky contacts on AlN/GaN and AlGaN/GaN heterostructures are fabricated.Based on the measured current–voltage and capacitance–voltage curves,the electrical characteristics of AlN/GaN Schottky diode,such as Schottky barrier height,turn-on voltage,reverse breakdown voltage,ideal factor,and the current-transport mechanism,are analyzed and then compared with those of an AlGaN/GaN diode by self-consistently solving Schrdinger’s and Poisson’s equations.It is found that the dislocation-governed tunneling is dominant for both AlN/GaN and AlGaN/GaN Schottky diodes.However,more dislocation defects and a thinner barrier layer for AlN/GaN heterostructure results in a larger tunneling probability,and causes a larger leakage current and lower reverse breakdown voltage,even though the Schottky barrier height of AlN/GaN Schottky diode is calculated to be higher that of an AlGaN/GaN diode.