Simulation of plasma doping process by using the localized molecular dynamics method

Plasma doping is the candidate for semiconductor doping. Accurate simulation of the doping technology is needed for the advanced integrated circuit manufacturing. In this paper, the plasma doping process simulation is performed by using the localized molecular dynamics method. Models that involve the statistics of the implanted compositions, angles and energies are developed. The effect of the model on simulation results is studied. The simulation results about the doping concentration profile are supported by experimental data.     

Vertical assembly of carbon nanotubes for via interconnects

The via interconnects are key components in ultra-large scale integrated circuits(ULSI).This paper deals with a new method to create single-walled carbon nanotubes(SWNTs) via interconnects using alternating dielectrophoresis(DEP).Carbon nanotubes are vertically assembled in the microscale via-holes successfully at room temperature under ambient condition.The electrical evaluation of the SWNT vias reveals that our DEP assembly technique is highly reliable and the success rate of assembly can be as high as 90%.We also propose and test possible approaches to reducing the contact resistance between CNT vias and metal electrodes.     

Fabricating GeO2passivation layer by N2O plasma oxidation for Ge NMOSFETs application

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that1.0-nm GeO2is achieved after 120-s N2O plasma oxidation at 300?C. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N2O plasma passivation is about ～ 3 × 1011cm-2·eV-1. With GeO2passivation,the hysteresis of metal–oxide–semiconductor(MOS) capacitor with Al2O3serving as gate dielectric is reduced to ～ 50 mV,compared with ～ 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.     

A novel 10-nm physical gate length double-gate junction field effect transisto

A novel double-gate （DG） junction field effect transistor （JFET） with depletion operation mode is proposed in this paper. Compared with the conventional DG MOSFET, the novel DG JFET can achieve excellent performance with square body design, which relaxes the requirement on silicon film thickness of DG devices. Moreover, due to the structural symmetry, both p-type and n-type devices can be realized on exactly the same structure, which greatly simplifies integration. It can reduce the delay by about 60% in comparison with the conventional DG MOSFETs.     

A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

In this paper, a complementary metal-oxide semiconductor （CMOS）-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon （SGPS） trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.     

Impact of the displacement damage in channel and source/drain regions on the DC characteristics degradation in deep-submicron MOSFETs after heavy ion irradiation

This paper mainly reports the permanent impact of displacement damage induced by heavy-ion strikes on the deep-submicron MOSFETs.Upon the heavy ion track through the device,it can lead to displacement damage,including the vacancies and the interstitials.As the featured size of device scales down,the damage can change the dopant distribution in the channel and source/drain regions through the generation of radiation-induced defects and thus have significant impacts on their electrical characteristics.The measured results show that the radiation-induced damage can cause DC characteristics degradations including the threshold voltage,subthreshold swing,saturation drain current,transconductance,etc.The radiation-induced displacement damage may become the dominant issue while it was the secondary concern for the traditional devices after the heavy ion irradiation.The samples are also irradiated by Co-60 gamma ray for comparison with the heavy ion irradiation results.Corresponding explanations and analysis are discussed.     

Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

Nitrogen plasma passivation(NPP) on(111) germanium(Ge) was studied in terms of the interface trap density,roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition(PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interfacial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness(EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.     

高迁移率Ge沟道器件研究进展

高迁移率Ge沟道器件由于其较高而且更对称的载流子迁移率, 成为未来互补型金属-氧化物-半导体(CMOS) 器件极有潜力的候选材料. 然而, 对于Ge基MOS器件, 其栅、源漏方面面临的挑战严重影响了Ge基MOS 器件性能的提升, 尤其是Ge NMOS器件. 本文重点分析了Ge基器件在栅、源漏方面面临的问题, 综述了国内外研究者们提出的不同解决方案, 在此基础上提出了新的技术方案. 研究结果为Ge基MOS 器件性能的进一步提升奠定了基础.     

超陡倒掺杂分布对超深亚微米金属-氧化物-半导体器件总剂量辐照特性的改善

分析了沟道中超陡倒掺杂和均匀掺杂两种情况下超深亚微米MOS器件的总剂量辐照特性,主要比较了两种掺杂分布的器件在辐照情况下的泄漏电流与阈值电压的退化特性.结果表明,在辐照剂量500krad情况下,超陡倒掺杂器件的泄漏电流比均匀掺杂器件的泄漏电流低2—3个量级;而在辐照剂量500krad情况下,由于器件俘获的空穴量饱和,超陡倒掺杂的改善没有那么明显.但超陡倒掺杂的阈值电压漂移量比均匀掺杂的情况小约40mV.超陡倒掺杂有利于改善器件的总剂量辐照特性.文中还给出了用于改善器件辐照特性的超陡倒掺杂分布的优化设计,为超深亚微米器件抗辐照加固提供了依据.     

面向产业需求的21世纪微电子技术的发展(上)

微电子产业是国民经济与国防建设的战略性基础产业．对此，我国经历了发展时期的奋斗，现正处于微电子产业迅速崛起的前夕，预计经过10—15年左右时间的努力，将把我国建设成为微电子产业和科学技术的强国．文章着重介绍了21世纪微电子产业的发展需求，面向这个需求，讨论了21世纪微电子科学技术的主要发展方向．认为：一方面，特征尺寸将继续等比例缩小(scaling down)，包括新结构、新工艺、新材料的器件设计与制备技术以及光刻技术、互连技术将迅速发展；基于特征尺寸继续等比例缩小，系统芯片(SOC)将取代目前的集成电路(IC)最终成为主流产品；另一方面，纳电子学也将得到突破性进展，量子器件、分子电子器件等的相关研究日益活跃，期望最终达到可集成的目标；此外，微电子技术与其他领域相结合诞生出的新的技术增长点和新的学科——微机电系统(MEMS)技术等也将继续快速发展．文章阐述了相关发展方向存在的挑战和可能的解决方案，对可能进一步开展的具有重要学术意义和应用价值的研究工作进行了探讨．