Fabricating GeO2passivation layer by N2O plasma oxidation for Ge NMOSFETs application

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that1.0-nm GeO2is achieved after 120-s N2O plasma oxidation at 300?C. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N2O plasma passivation is about ～ 3 × 1011cm-2·eV-1. With GeO2passivation,the hysteresis of metal–oxide–semiconductor(MOS) capacitor with Al2O3serving as gate dielectric is reduced to ～ 50 mV,compared with ～ 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.     

Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

Nitrogen plasma passivation(NPP) on(111) germanium(Ge) was studied in terms of the interface trap density,roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition(PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interfacial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness(EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.     

Fabricating GeO2 passivation layer by N20 plasma oxidation for Ge NMOSFETs application

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 cm-2.eV-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor （MOS） capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.     

高迁移率Ge沟道器件研究进展

高迁移率Ge沟道器件由于其较高而且更对称的载流子迁移率, 成为未来互补型金属-氧化物-半导体(CMOS) 器件极有潜力的候选材料. 然而, 对于Ge基MOS器件, 其栅、源漏方面面临的挑战严重影响了Ge基MOS 器件性能的提升, 尤其是Ge NMOS器件. 本文重点分析了Ge基器件在栅、源漏方面面临的问题, 综述了国内外研究者们提出的不同解决方案, 在此基础上提出了新的技术方案. 研究结果为Ge基MOS 器件性能的进一步提升奠定了基础.     

Theoretical and experimental analysis of the effects of the series resistance on luminous efficacy in GaN-based light emitting diodes

In this paper, a new equivalent circuit model of GaN-based light emitting diodes （LEDs） is established. The impact of the series resistance to luminous efficacy is simulated using the MATLAB software. GaN-based LEDs with different n- contact electrode materials （LEDs with Ni/Au and LEDs with Cr/Au） are fabricated. By comparing and analyzing the results of performances, we concluded that both the series resistance and the carrier loss could affect the luminous efficacy severely. LEDs with lower series resistance have higher luminous efficacy and its efficiency droop is alleviated simultaneously. To improve luminous efficacy, the fabrication process should be optimized for lower series resistance.     

Experimental clarification of orientation dependence of germanium PMOSFETs with AlzO3/GeOx/Ge gate stack

An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is （110）〉（111） ~ （100）, and the best channel direction is （110）/[110]. Moreover, the （110） device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while （100） and （111） devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.